Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 1ddeb625 authored by Tom St Denis's avatar Tom St Denis Committed by Alex Deucher
Browse files

drm/amd/powerplay: move clockgating to after ungating power in pp for uvd/vce 



Cannot set clockgating state before ungating power.

Signed-off-by: default avatarTom St Denis <tom.stdenis@amd.com>
Reviewed-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 09fc7eff

drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c

+7 −7
Original line number Diff line number Diff line
@@ -177,12 +177,12 @@ int cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) 
		cz_dpm_powerdown_uvd(hwmgr);

	} else {

		cz_dpm_powerup_uvd(hwmgr);

		cgs_set_clockgating_state(hwmgr->device,

						AMD_IP_BLOCK_TYPE_UVD,

						AMD_PG_STATE_GATE);

		cgs_set_powergating_state(hwmgr->device,

						AMD_IP_BLOCK_TYPE_UVD,

						AMD_CG_STATE_UNGATE);

		cgs_set_clockgating_state(hwmgr->device,

						AMD_IP_BLOCK_TYPE_UVD,

						AMD_PG_STATE_GATE);

		cz_dpm_update_uvd_dpm(hwmgr, false);

	}
@@ -211,14 +211,14 @@ int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate) 
			} else {

				cz_dpm_powerup_vce(hwmgr);

				cz_hwmgr->vce_power_gated = false;

				cgs_set_clockgating_state(

							hwmgr->device,

							AMD_IP_BLOCK_TYPE_VCE,

							AMD_PG_STATE_GATE);

				cgs_set_powergating_state(

							hwmgr->device,

							AMD_IP_BLOCK_TYPE_VCE,

							AMD_CG_STATE_UNGATE);

				cgs_set_clockgating_state(

							hwmgr->device,

							AMD_IP_BLOCK_TYPE_VCE,

							AMD_PG_STATE_GATE);

				cz_dpm_update_vce_dpm(hwmgr);

				cz_enable_disable_vce_dpm(hwmgr, true);

				return 0;