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Commit 1dce6f5b authored by Charan Teja Reddy's avatar Charan Teja Reddy
Browse files

iommu/arm-smmu: add option to enable static context bank allocation 



To implement slave side protection, programming of global registers as
well as secure context bank registers is handed over to TZ. Now, instead
of dynamically allocating context banks, TZ allocates CBs once in pre
defined static manner during boot and this allocation is maintained
throughout the life of system.

Add an option to enable use of this pre-defined context bank allocation.
We would be reading through SMR and S2CR registers at run time to
identify CB allocated for a particular sid.

Change-Id: If0b86bd89b0422c2170551de0d2f6405a79fc255
Signed-off-by: default avatarCharan Teja Reddy <charante@codeaurora.org>
parent bcd97ef7

Documentation/devicetree/bindings/iommu/arm,smmu.txt

+9 −0
Original line number Diff line number Diff line
@@ -101,6 +101,15 @@ conditions. 
		  Any sid X for which X&~mask==sid will be programmed with the

		  given actlr-setting.



- qcom,enable-static-cb : Enables option to use pre-defined static context bank

		  allocation programmed by TZ. Global register including SMR and

		  S2CR registers are configured by TZ before kernel comes up and

		  this programming is not altered throughout the life of system.

		  We would be reading through these registers at run time to

		  identify CB allocated for a particular sid. SID masking isn't

		  supported as we are directly comparing client SID with ID bits

		  of SMR registers.



- qcom,deferred-regulator-disable-delay : The time delay for deferred regulator

                  disable in ms. In case of unmap call, regulator is

                  enabled/disabled. This may introduce additional delay. For

drivers/iommu/arm-smmu.c

+10 −1
Original line number Diff line number Diff line
@@ -248,6 +248,7 @@ struct arm_smmu_device { 
#define ARM_SMMU_OPT_DYNAMIC		(1 << 3)

#define ARM_SMMU_OPT_3LVL_TABLES	(1 << 4)

#define ARM_SMMU_OPT_NO_ASID_RETENTION	(1 << 5)

#define ARM_SMMU_OPT_STATIC_CB		(1 << 6)

	u32				options;

	enum arm_smmu_arch_version	version;

	enum arm_smmu_implementation	model;
@@ -379,6 +380,7 @@ static struct arm_smmu_option_prop arm_smmu_options[] = { 
	{ ARM_SMMU_OPT_DYNAMIC, "qcom,dynamic" },

	{ ARM_SMMU_OPT_3LVL_TABLES, "qcom,use-3-lvl-tables" },

	{ ARM_SMMU_OPT_NO_ASID_RETENTION, "qcom,no-asid-retention" },

	{ ARM_SMMU_OPT_STATIC_CB, "qcom,enable-static-cb"},

	{ 0, NULL},

};
@@ -402,6 +404,8 @@ static int arm_smmu_alloc_cb(struct iommu_domain *domain, 
				struct arm_smmu_device *smmu,

				struct device *dev);



static bool arm_smmu_is_static_cb(struct arm_smmu_device *smmu);



static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom)

{

	return container_of(dom, struct arm_smmu_domain, domain);
@@ -439,6 +443,11 @@ static bool is_iommu_pt_coherent(struct arm_smmu_domain *smmu_domain) 
		return false;

}



static bool arm_smmu_is_static_cb(struct arm_smmu_device *smmu)

{

	return smmu->options & ARM_SMMU_OPT_STATIC_CB;

}



static bool arm_smmu_is_domain_secure(struct arm_smmu_domain *smmu_domain)

{

	return (smmu_domain->secure_vmid != VMID_INVAL);
@@ -3592,7 +3601,7 @@ static int arm_smmu_alloc_cb(struct iommu_domain *domain, 
			cb = smmu->s2crs[idx].cbndx;

	}



	if (cb < 0) {

	if (cb < 0 && !arm_smmu_is_static_cb(smmu)) {

		mutex_unlock(&smmu->stream_map_mutex);

		return __arm_smmu_alloc_bitmap(smmu->context_map,

						smmu->num_s2_context_banks,