x86: remove mach_apic.h (1dcdd3d1) · Commits · e / devices / android_kernel_oneplus_sm8150

arch/x86/include/asm/genapic.h

+139 −0

Original line number	Diff line number	Diff line
		@@ -120,4 +120,143 @@ static inline void default_wait_for_init_deassert(atomic_t *deassert)
		return;
		}

		extern void generic_bigsmp_probe(void);


		#ifdef CONFIG_X86_LOCAL_APIC

		#include <asm/smp.h>

		#define APIC_DFR_VALUE (APIC_DFR_FLAT)

		static inline const struct cpumask *default_target_cpus(void)
		{
		#ifdef CONFIG_SMP
		return cpu_online_mask;
		#else
		return cpumask_of(0);
		#endif
		}

		DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid);


		static inline unsigned int read_apic_id(void)
		{
		unsigned int reg;

		reg = (u32 )(APIC_BASE + APIC_ID);

		return apic->get_apic_id(reg);
		}

		#ifdef CONFIG_X86_64
		extern void default_setup_apic_routing(void);
		#else

		/*
		* Set up the logical destination ID.
		*
		* Intel recommends to set DFR, LDR and TPR before enabling
		* an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
		* document number 292116). So here it goes...
		*/
		extern void default_init_apic_ldr(void);

		static inline int default_apic_id_registered(void)
		{
		return physid_isset(read_apic_id(), phys_cpu_present_map);
		}

		static inline unsigned int
		default_cpu_mask_to_apicid(const struct cpumask *cpumask)
		{
		return cpumask_bits(cpumask)[0];
		}

		static inline unsigned int
		default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
		const struct cpumask *andmask)
		{
		unsigned long mask1 = cpumask_bits(cpumask)[0];
		unsigned long mask2 = cpumask_bits(andmask)[0];
		unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];

		return (unsigned int)(mask1 & mask2 & mask3);
		}

		static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
		{
		return cpuid_apic >> index_msb;
		}

		static inline void default_setup_apic_routing(void)
		{
		#ifdef CONFIG_X86_IO_APIC
		printk("Enabling APIC mode: %s. Using %d I/O APICs\n",
		"Flat", nr_ioapics);
		#endif
		}

		extern int default_apicid_to_node(int logical_apicid);

		#endif

		static inline unsigned long default_check_apicid_used(physid_mask_t bitmap, int apicid)
		{
		return physid_isset(apicid, bitmap);
		}

		static inline unsigned long default_check_apicid_present(int bit)
		{
		return physid_isset(bit, phys_cpu_present_map);
		}

		static inline physid_mask_t default_ioapic_phys_id_map(physid_mask_t phys_map)
		{
		return phys_map;
		}

		/* Mapping from cpu number to logical apicid */
		static inline int default_cpu_to_logical_apicid(int cpu)
		{
		return 1 << cpu;
		}

		static inline int __default_cpu_present_to_apicid(int mps_cpu)
		{
		if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
		return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
		else
		return BAD_APICID;
		}

		static inline int
		__default_check_phys_apicid_present(int boot_cpu_physical_apicid)
		{
		return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map);
		}

		#ifdef CONFIG_X86_32
		static inline int default_cpu_present_to_apicid(int mps_cpu)
		{
		return __default_cpu_present_to_apicid(mps_cpu);
		}

		static inline int
		default_check_phys_apicid_present(int boot_cpu_physical_apicid)
		{
		return __default_check_phys_apicid_present(boot_cpu_physical_apicid);
		}
		#else
		extern int default_cpu_present_to_apicid(int mps_cpu);
		extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid);
		#endif

		static inline physid_mask_t default_apicid_to_cpu_present(int phys_apicid)
		{
		return physid_mask_of_physid(phys_apicid);
		}

		#endif /* CONFIG_X86_LOCAL_APIC */
		#endif /* _ASM_X86_GENAPIC_64_H */

arch/x86/include/asm/mach-default/mach_apic.h

deleted100644 → 0

+0 −144

Original line number	Diff line number	Diff line
		#ifndef _ASM_X86_MACH_DEFAULT_MACH_APIC_H
		#define _ASM_X86_MACH_DEFAULT_MACH_APIC_H

		#ifdef CONFIG_X86_LOCAL_APIC

		#include <asm/smp.h>

		#define APIC_DFR_VALUE (APIC_DFR_FLAT)

		static inline const struct cpumask *default_target_cpus(void)
		{
		#ifdef CONFIG_SMP
		return cpu_online_mask;
		#else
		return cpumask_of(0);
		#endif
		}

		#ifdef CONFIG_X86_64
		#include <asm/genapic.h>
		#define read_apic_id() (apic->get_apic_id(apic_read(APIC_ID)))
		extern void default_setup_apic_routing(void);
		#else
		/*
		* Set up the logical destination ID.
		*
		* Intel recommends to set DFR, LDR and TPR before enabling
		* an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
		* document number 292116). So here it goes...
		*/
		static inline void default_init_apic_ldr(void)
		{
		unsigned long val;

		apic_write(APIC_DFR, APIC_DFR_VALUE);
		val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
		val \|= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
		apic_write(APIC_LDR, val);
		}

		static inline int default_apic_id_registered(void)
		{
		return physid_isset(read_apic_id(), phys_cpu_present_map);
		}

		static inline unsigned int
		default_cpu_mask_to_apicid(const struct cpumask *cpumask)
		{
		return cpumask_bits(cpumask)[0];
		}

		static inline unsigned int
		default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
		const struct cpumask *andmask)
		{
		unsigned long mask1 = cpumask_bits(cpumask)[0];
		unsigned long mask2 = cpumask_bits(andmask)[0];
		unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];

		return (unsigned int)(mask1 & mask2 & mask3);
		}

		static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
		{
		return cpuid_apic >> index_msb;
		}

		static inline void default_setup_apic_routing(void)
		{
		#ifdef CONFIG_X86_IO_APIC
		printk("Enabling APIC mode: %s. Using %d I/O APICs\n",
		"Flat", nr_ioapics);
		#endif
		}

		static inline int default_apicid_to_node(int logical_apicid)
		{
		#ifdef CONFIG_SMP
		return apicid_2_node[hard_smp_processor_id()];
		#else
		return 0;
		#endif
		}

		#endif

		static inline unsigned long default_check_apicid_used(physid_mask_t bitmap, int apicid)
		{
		return physid_isset(apicid, bitmap);
		}

		static inline unsigned long default_check_apicid_present(int bit)
		{
		return physid_isset(bit, phys_cpu_present_map);
		}

		static inline physid_mask_t default_ioapic_phys_id_map(physid_mask_t phys_map)
		{
		return phys_map;
		}

		/* Mapping from cpu number to logical apicid */
		static inline int default_cpu_to_logical_apicid(int cpu)
		{
		return 1 << cpu;
		}

		static inline int __default_cpu_present_to_apicid(int mps_cpu)
		{
		if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
		return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
		else
		return BAD_APICID;
		}

		static inline int
		__default_check_phys_apicid_present(int boot_cpu_physical_apicid)
		{
		return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map);
		}

		#ifdef CONFIG_X86_32
		static inline int default_cpu_present_to_apicid(int mps_cpu)
		{
		return __default_cpu_present_to_apicid(mps_cpu);
		}

		static inline int
		default_check_phys_apicid_present(int boot_cpu_physical_apicid)
		{
		return __default_check_phys_apicid_present(boot_cpu_physical_apicid);
		}
		#else
		extern int default_cpu_present_to_apicid(int mps_cpu);
		extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid);
		#endif

		static inline physid_mask_t default_apicid_to_cpu_present(int phys_apicid)
		{
		return physid_mask_of_physid(phys_apicid);
		}

		#endif /* CONFIG_X86_LOCAL_APIC */
		#endif /* _ASM_X86_MACH_DEFAULT_MACH_APIC_H */

arch/x86/include/asm/mach-generic/mach_apic.h

deleted100644 → 0

+0 −8

Original line number	Diff line number	Diff line
		#ifndef _ASM_X86_MACH_GENERIC_MACH_APIC_H
		#define _ASM_X86_MACH_GENERIC_MACH_APIC_H

		#include <asm/genapic.h>

		extern void generic_bigsmp_probe(void);

		#endif /* _ASM_X86_MACH_GENERIC_MACH_APIC_H */

arch/x86/include/asm/smp.h

+0 −19

Original line number	Diff line number	Diff line
		@@ -173,8 +173,6 @@ extern int safe_smp_processor_id(void);

		#endif

		#include <asm/genapic.h>

		#ifdef CONFIG_X86_LOCAL_APIC

		#ifndef CONFIG_X86_64
		@@ -184,26 +182,9 @@ static inline int logical_smp_processor_id(void)
		return GET_APIC_LOGICAL_ID((u32 )(APIC_BASE + APIC_LDR));
		}

		static inline unsigned int read_apic_id(void)
		{
		unsigned int reg;

		reg = (u32 )(APIC_BASE + APIC_ID);

		return apic->get_apic_id(reg);
		}
		#endif


		# if defined(APIC_DEFINITION) \|\| defined(CONFIG_X86_64)
		extern int hard_smp_processor_id(void);
		# else
		static inline int hard_smp_processor_id(void)
		{
		/* we don't want to mark this access volatile - bad code generation */
		return read_apic_id();
		}
		# endif /* APIC_DEFINITION */

		#else /* CONFIG_X86_LOCAL_APIC */

arch/x86/kernel/acpi/boot.c

+1 −13

Original line number	Diff line number	Diff line
		@@ -42,10 +42,6 @@
		#include <asm/mpspec.h>
		#include <asm/smp.h>

		#ifdef CONFIG_X86_LOCAL_APIC
		# include <mach_apic.h>
		#endif

		static int __initdata acpi_force = 0;
		u32 acpi_rsdt_forced;
		#ifdef CONFIG_ACPI
		@@ -56,15 +52,7 @@ int acpi_disabled = 1;
		EXPORT_SYMBOL(acpi_disabled);

		#ifdef CONFIG_X86_64

		# include <asm/proto.h>

		#else /* X86 */

		#ifdef CONFIG_X86_LOCAL_APIC
		#include <mach_apic.h>
		#endif /* CONFIG_X86_LOCAL_APIC */

		#endif /* X86 */

		#define BAD_MADT_ENTRY(entry, end) ( \