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Commit 1d8e1c75 authored by Chris Wilson's avatar Chris Wilson Committed by Eric Anholt
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drm/i915: Enable aspect/centering panel fitting for Ironlake.



v2: Hook in DP paths to keep FULLSCREEN panel fitting on eDP.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
parent 2e88e40b
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+1 −0
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o i915_mem.o \
	  intel_hdmi.o \
	  intel_sdvo.o \
	  intel_modes.o \
	  intel_panel.o \
	  intel_i2c.o \
	  intel_fb.o \
	  intel_tv.o \
+2 −0
Original line number Diff line number Diff line
@@ -614,6 +614,8 @@ typedef struct drm_i915_private {
	struct sdvo_device_mapping sdvo_mappings[2];
	/* indicate whether the LVDS_BORDER should be enabled or not */
	unsigned int lvds_border_bits;
	/* Panel fitter placement and size for Ironlake+ */
	u32 pch_pf_pos, pch_pf_size;

	struct drm_crtc *plane_to_crtc_mapping[2];
	struct drm_crtc *pipe_to_crtc_mapping[2];
+7 −9
Original line number Diff line number Diff line
@@ -2005,15 +2005,13 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
		/* Enable panel fitting for LVDS */
		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
		    || HAS_eDP || intel_pch_has_edp(crtc)) {
			if (dev_priv->pch_pf_size) {
				temp = I915_READ(pf_ctl_reg);
				I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);

			/* currently full aspect */
			I915_WRITE(pf_win_pos, 0);

			I915_WRITE(pf_win_size,
				   (dev_priv->panel_fixed_mode->hdisplay << 16) |
				   (dev_priv->panel_fixed_mode->vdisplay));
				I915_WRITE(pf_win_pos, dev_priv->pch_pf_pos);
				I915_WRITE(pf_win_size, dev_priv->pch_pf_size);
			} else
				I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
		}

		/* Enable CPU pipe */
+5 −15
Original line number Diff line number Diff line
@@ -523,21 +523,9 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,

	if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) &&
	    dev_priv->panel_fixed_mode) {
		struct drm_display_mode *fixed_mode = dev_priv->panel_fixed_mode;

		adjusted_mode->hdisplay = fixed_mode->hdisplay;
		adjusted_mode->hsync_start = fixed_mode->hsync_start;
		adjusted_mode->hsync_end = fixed_mode->hsync_end;
		adjusted_mode->htotal = fixed_mode->htotal;

		adjusted_mode->vdisplay = fixed_mode->vdisplay;
		adjusted_mode->vsync_start = fixed_mode->vsync_start;
		adjusted_mode->vsync_end = fixed_mode->vsync_end;
		adjusted_mode->vtotal = fixed_mode->vtotal;

		adjusted_mode->clock = fixed_mode->clock;
		drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);

		intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
		intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
					mode, adjusted_mode);
		/*
		 * the mode->clock is used to calculate the Data&Link M/N
		 * of the pipe. For the eDP the fixed clock should be used.
@@ -572,8 +560,10 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
			      "count %d clock %d\n",
			      intel_dp->link_bw, intel_dp->lane_count,
			      adjusted_mode->clock);

		return true;
	}

	return false;
}

+7 −0
Original line number Diff line number Diff line
@@ -186,6 +186,13 @@ extern bool intel_dpd_is_edp(struct drm_device *dev);
extern void intel_edp_link_config (struct intel_encoder *, int *, int *);


extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
				   struct drm_display_mode *adjusted_mode);
extern void intel_pch_panel_fitting(struct drm_device *dev,
				    int fitting_mode,
				    struct drm_display_mode *mode,
				    struct drm_display_mode *adjusted_mode);

extern int intel_panel_fitter_pipe (struct drm_device *dev);
extern void intel_crtc_load_lut(struct drm_crtc *crtc);
extern void intel_encoder_prepare (struct drm_encoder *encoder);
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