Merge "msm: ipa3: Embellish IPA/GSI support for IPA 4.5 emulation system" (1be41058) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/platform/msm/gsi/gsi.c

+87 −29

Original line number	Diff line number	Diff line
		@@ -822,6 +822,50 @@ int gsi_complete_clk_grant(unsigned long dev_hdl)
		}
		EXPORT_SYMBOL(gsi_complete_clk_grant);

		int gsi_map_base(phys_addr_t gsi_base_addr, u32 gsi_size)
		{
		if (!gsi_ctx) {
		pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__);
		return -GSI_STATUS_NODEV;
		}

		gsi_ctx->base = devm_ioremap_nocache(
		gsi_ctx->dev, gsi_base_addr, gsi_size);

		if (!gsi_ctx->base) {
		GSIERR("failed to map access to GSI HW\n");
		return -GSI_STATUS_RES_ALLOC_FAILURE;
		}

		GSIDBG("GSI base(%pa) mapped to (%pK) with len (0x%x)\n",
		&gsi_base_addr,
		gsi_ctx->base,
		gsi_size);

		return 0;
		}
		EXPORT_SYMBOL(gsi_map_base);

		int gsi_unmap_base(void)
		{
		if (!gsi_ctx) {
		pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__);
		return -GSI_STATUS_NODEV;
		}

		if (!gsi_ctx->base) {
		GSIERR("access to GSI HW has not been mapped\n");
		return -GSI_STATUS_INVALID_PARAMS;
		}

		devm_iounmap(gsi_ctx->dev, gsi_ctx->base);

		gsi_ctx->base = NULL;

		return 0;
		}
		EXPORT_SYMBOL(gsi_unmap_base);

		int gsi_register_device(struct gsi_per_props props, unsigned long dev_hdl)
		{
		int res;
		@@ -926,18 +970,16 @@ int gsi_register_device(struct gsi_per_props props, unsigned long dev_hdl)
		return -GSI_STATUS_UNSUPPORTED_OP;
		}

		gsi_ctx->base = devm_ioremap_nocache(gsi_ctx->dev, props->phys_addr,
		props->size);
		/*
		* If base not previously mapped via gsi_map_base(), map it
		* now...
		*/
		if (!gsi_ctx->base) {
		GSIERR("failed to remap GSI HW\n");
		return -GSI_STATUS_RES_ALLOC_FAILURE;
		res = gsi_map_base(props->phys_addr, props->size);
		if (res)
		return res;
		}

		GSIDBG("GSI base(%pa) mapped to (%pK) with len (0x%lx)\n",
		&(props->phys_addr),
		gsi_ctx->base,
		props->size);

		if (running_emulation) {
		GSIDBG("GSI SW ver register value 0x%x\n",
		gsi_readl(gsi_ctx->base +
		@@ -952,7 +994,7 @@ int gsi_register_device(struct gsi_per_props props, unsigned long dev_hdl)
		if (!gsi_ctx->intcntrlr_base) {
		GSIERR(
		"failed to remap emulator's interrupt controller HW\n");
		devm_iounmap(gsi_ctx->dev, gsi_ctx->base);
		gsi_unmap_base();
		devm_free_irq(gsi_ctx->dev, props->irq, gsi_ctx);
		return -GSI_STATUS_RES_ALLOC_FAILURE;
		}
		@@ -975,7 +1017,7 @@ int gsi_register_device(struct gsi_per_props props, unsigned long dev_hdl)
		atomic_set(&gsi_ctx->num_evt_ring, 0);
		gsi_ctx->max_ch = gsi_get_max_channels(gsi_ctx->per.ver);
		if (gsi_ctx->max_ch == 0) {
		devm_iounmap(gsi_ctx->dev, gsi_ctx->base);
		gsi_unmap_base();
		if (running_emulation)
		devm_iounmap(gsi_ctx->dev, gsi_ctx->intcntrlr_base);
		gsi_ctx->base = gsi_ctx->intcntrlr_base = NULL;
		@@ -985,7 +1027,7 @@ int gsi_register_device(struct gsi_per_props props, unsigned long dev_hdl)
		}
		gsi_ctx->max_ev = gsi_get_max_event_rings(gsi_ctx->per.ver);
		if (gsi_ctx->max_ev == 0) {
		devm_iounmap(gsi_ctx->dev, gsi_ctx->base);
		gsi_unmap_base();
		if (running_emulation)
		devm_iounmap(gsi_ctx->dev, gsi_ctx->intcntrlr_base);
		gsi_ctx->base = gsi_ctx->intcntrlr_base = NULL;
		@@ -1001,7 +1043,7 @@ int gsi_register_device(struct gsi_per_props props, unsigned long dev_hdl)

		if (props->mhi_er_id_limits_valid &&
		props->mhi_er_id_limits[0] > (gsi_ctx->max_ev - 1)) {
		devm_iounmap(gsi_ctx->dev, gsi_ctx->base);
		gsi_unmap_base();
		if (running_emulation)
		devm_iounmap(gsi_ctx->dev, gsi_ctx->intcntrlr_base);
		gsi_ctx->base = gsi_ctx->intcntrlr_base = NULL;
		@@ -1052,7 +1094,7 @@ int gsi_register_device(struct gsi_per_props props, unsigned long dev_hdl)
		res = setup_emulator_cntrlr(
		gsi_ctx->intcntrlr_base, gsi_ctx->intcntrlr_mem_size);
		if (res != 0) {
		devm_iounmap(gsi_ctx->dev, gsi_ctx->base);
		gsi_unmap_base();
		devm_iounmap(gsi_ctx->dev, gsi_ctx->intcntrlr_base);
		gsi_ctx->base = gsi_ctx->intcntrlr_base = NULL;
		devm_free_irq(gsi_ctx->dev, props->irq, gsi_ctx);
		@@ -1149,7 +1191,7 @@ int gsi_deregister_device(unsigned long dev_hdl, bool force)
		__gsi_config_gen_irq(gsi_ctx->per.ee, ~0, 0);

		devm_free_irq(gsi_ctx->dev, gsi_ctx->per.irq, gsi_ctx);
		devm_iounmap(gsi_ctx->dev, gsi_ctx->base);
		gsi_unmap_base();
		memset(gsi_ctx, 0, sizeof(*gsi_ctx));

		return GSI_STATUS_SUCCESS;
		@@ -3240,32 +3282,28 @@ static void gsi_configure_bck_prs_matrix(void *base)
		gsi_base + GSI_IC_UCONTROLLER_GPR_BCK_PRS_MSB_OFFS);
		}

		int gsi_configure_regs(phys_addr_t gsi_base_addr, u32 gsi_size,
		phys_addr_t per_base_addr, enum gsi_ver ver)
		int gsi_configure_regs(phys_addr_t per_base_addr, enum gsi_ver ver)
		{
		void __iomem *gsi_base;

		if (!gsi_ctx) {
		pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__);
		return -GSI_STATUS_NODEV;
		}

		if (!gsi_ctx->base) {
		GSIERR("access to GSI HW has not been mapped\n");
		return -GSI_STATUS_INVALID_PARAMS;
		}

		if (ver <= GSI_VER_ERR \|\| ver >= GSI_VER_MAX) {
		GSIERR("Incorrect version %d\n", ver);
		return -GSI_STATUS_ERROR;
		}

		gsi_base = ioremap_nocache(gsi_base_addr, gsi_size);
		if (!gsi_base) {
		GSIERR("ioremap failed\n");
		return -GSI_STATUS_RES_ALLOC_FAILURE;
		}
		gsi_writel(0, gsi_base + GSI_GSI_PERIPH_BASE_ADDR_MSB_OFFS);
		gsi_writel(0, gsi_ctx->base + GSI_GSI_PERIPH_BASE_ADDR_MSB_OFFS);
		gsi_writel(per_base_addr,
		gsi_base + GSI_GSI_PERIPH_BASE_ADDR_LSB_OFFS);
		gsi_configure_bck_prs_matrix((void *)gsi_base);
		gsi_configure_ieps(gsi_base, ver);
		iounmap(gsi_base);
		gsi_ctx->base + GSI_GSI_PERIPH_BASE_ADDR_LSB_OFFS);
		gsi_configure_bck_prs_matrix((void *)gsi_ctx->base);
		gsi_configure_ieps(gsi_ctx->base, ver);

		return 0;
		}
		@@ -3440,6 +3478,26 @@ int gsi_halt_channel_ee(unsigned int chan_idx, unsigned int ee, int *code)
		}
		EXPORT_SYMBOL(gsi_halt_channel_ee);

		int gsi_map_virtual_ch_to_per_ep(u32 ee, u32 chan_num, u32 per_ep_index)
		{
		if (!gsi_ctx) {
		pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__);
		return -GSI_STATUS_NODEV;
		}

		if (!gsi_ctx->base) {
		GSIERR("access to GSI HW has not been mapped\n");
		return -GSI_STATUS_INVALID_PARAMS;
		}

		gsi_writel(per_ep_index,
		gsi_ctx->base +
		GSI_V2_5_GSI_MAP_EE_n_CH_k_VP_TABLE_OFFS(chan_num, ee));

		return 0;
		}
		EXPORT_SYMBOL(gsi_map_virtual_ch_to_per_ep);

		static int msm_gsi_probe(struct platform_device *pdev)
		{
		struct device *dev = &pdev->dev;

drivers/platform/msm/ipa/ipa_v3/ipa.c

+25 −5

Original line number	Diff line number	Diff line
		@@ -4426,10 +4426,10 @@ static int ipa3_gsi_pre_fw_load_init(void)
		{
		int result;

		result = gsi_configure_regs(ipa3_res.transport_mem_base,
		ipa3_res.transport_mem_size,
		result = gsi_configure_regs(
		ipa3_res.ipa_mem_base,
		ipa3_get_gsi_ver(ipa3_res.ipa_hw_type));

		if (result) {
		IPAERR("Failed to configure GSI registers\n");
		return -EINVAL;
		@@ -4761,6 +4761,9 @@ static int ipa3_manual_load_ipa_fws(void)
		case IPA_HW_v4_0:
		path = IPA_FWS_PATH_4_0;
		break;
		case IPA_HW_v4_5:
		path = IPA_FWS_PATH_4_5;
		break;
		default:
		break;
		}
		@@ -5233,10 +5236,24 @@ static int ipa3_pre_init(const struct ipa3_plat_drv_res *resource_p,
		ipa3_ctx->mmio,
		resource_p->ipa_mem_size);

		/*
		* Since we now know where the transport's registers live,
		* let's set up access to them. This is done since subseqent
		* functions, that deal with the transport, require the
		* access.
		*/
		if (gsi_map_base(
		ipa3_res.transport_mem_base,
		ipa3_res.transport_mem_size) != 0) {
		IPAERR("Allocation of gsi base failed\n");
		result = -EFAULT;
		goto fail_gsi_map;
		}

		/*
		* In Virtual and Emulation mode, IPAHAL used to load the
		* firmwares and there is no SMMU so IPAHAL is initialized
		* here
		* here.
		*/
		if (ipa3_ctx->ipa3_hw_mode == IPA_HW_MODE_VIRTUAL \|\|
		ipa3_ctx->ipa3_hw_mode == IPA_HW_MODE_EMULATION) {
		@@ -5546,6 +5563,8 @@ static int ipa3_pre_init(const struct ipa3_plat_drv_res *resource_p,
		ipa3_ctx->ipa3_hw_mode == IPA_HW_MODE_EMULATION)
		ipahal_destroy();
		fail_ipahal_init:
		gsi_unmap_base();
		fail_gsi_map:
		iounmap(ipa3_ctx->mmio);
		fail_remap:
		ipa3_disable_clks();
		@@ -6981,10 +7000,11 @@ MODULE_DESCRIPTION("IPA HW device driver");

		/*
		* Module parameter. Invoke as follows:
		* insmod ipat.ko emulation_type=[13\|14\|...\|N]
		* insmod ipat.ko emulation_type=[13\|14\|17\|...\|N]
		* Examples:
		* insmod ipat.ko emulation_type=13 # for IPA 3.5.1
		* insmod ipat.ko emulation_type=14 # for IPA 4.0
		* insmod ipat.ko emulation_type=17 # for IPA 4.5
		*
		* NOTE: The emulation_type values need to come from: enum ipa_hw_type
		*
		@@ -6993,4 +7013,4 @@ MODULE_DESCRIPTION("IPA HW device driver");
		module_param(emulation_type, uint, 0000);
		MODULE_PARM_DESC(
		emulation_type,
		"IPA emulation type (Use 13 for IPA 3.5.1, 14 for IPA 4.0)");
		"emulation_type=N N can be 13 for IPA 3.5.1, 14 for IPA 4.0, 17 for IPA 4.5");

drivers/platform/msm/ipa/ipa_v3/ipa_dt_replacement.c

+158 −55

Original line number	Diff line number	Diff line
		@@ -26,6 +26,7 @@
		enum dtsi_index_e {
		DTSI_INDEX_3_5_1 = 0,
		DTSI_INDEX_4_0 = 1,
		DTSI_INDEX_4_5 = 2,
		};

		struct dtsi_replacement_u32 {
		@@ -65,12 +66,28 @@ struct dtsi_replacement_resource_table {
		};

		/*
		* Any of the data below with _4_5 in the name represent data taken
		* from the 4.5 dtsi file.
		*
		* Any of the data below with _4_0 in the name represent data taken
		* from the 4.0 dtsi file.
		*
		* Any of the data below with _3_5_1 in the name represent data taken
		* from the 3.5.1 dtsi file.
		*/
		static struct dtsi_replacement_bool ipa3_plat_drv_bool_4_5[] = {
		{"qcom,use-ipa-tethering-bridge", true},
		{"qcom,modem-cfg-emb-pipe-flt", true},
		{"qcom,ipa-wdi2", false},
		{"qcom,use-64-bit-dma-mask", false},
		{"qcom,bandwidth-vote-for-ipa", true},
		{"qcom,skip-uc-pipe-reset", false},
		{"qcom,tethered-flow-control", false},
		{"qcom,use-rg10-limitation-mitigation", false},
		{"qcom,do-not-use-ch-gsi-20", false},
		{"qcom,use-ipa-pm", true},
		};

		static struct dtsi_replacement_bool ipa3_plat_drv_bool_4_0[] = {
		{"qcom,use-ipa-tethering-bridge", true},
		{"qcom,modem-cfg-emb-pipe-flt", true},
		@@ -103,6 +120,18 @@ ipa3_plat_drv_bool_table[] = {
		ARRAY_SIZE(ipa3_plat_drv_bool_3_5_1) },
		{ ipa3_plat_drv_bool_4_0,
		ARRAY_SIZE(ipa3_plat_drv_bool_4_0) },
		{ ipa3_plat_drv_bool_4_5,
		ARRAY_SIZE(ipa3_plat_drv_bool_4_5) },
		};

		static struct dtsi_replacement_u32 ipa3_plat_drv_u32_4_5[] = {
		{"qcom,ipa-hw-ver", IPA_HW_v4_5},
		{"qcom,ipa-hw-mode", 3},
		{"qcom,wan-rx-ring-size", 192},
		{"qcom,lan-rx-ring-size", 192},
		{"qcom,ee", 0},
		{"qcom,msm-bus,num-cases", 5},
		{"emulator-bar0-offset", 0x01C00000},
		};

		static struct dtsi_replacement_u32 ipa3_plat_drv_u32_4_0[] = {
		@@ -128,6 +157,12 @@ static struct dtsi_replacement_u32_table ipa3_plat_drv_u32_table[] = {
		ARRAY_SIZE(ipa3_plat_drv_u32_3_5_1) },
		{ ipa3_plat_drv_u32_4_0,
		ARRAY_SIZE(ipa3_plat_drv_u32_4_0) },
		{ ipa3_plat_drv_u32_4_5,
		ARRAY_SIZE(ipa3_plat_drv_u32_4_5) },
		};

		static u32 mhi_event_ring_id_limits_array_4_5[] = {
		9, 10
		};

		static u32 mhi_event_ring_id_limits_array_4_0[] = {
		@@ -138,51 +173,32 @@ static u32 mhi_event_ring_id_limits_array_3_5_1[] = {
		IPA_MHI_GSI_EVENT_RING_ID_START, IPA_MHI_GSI_EVENT_RING_ID_END
		};

		static u32 ipa_tz_unlock_reg_array_4_0[] = {
		static u32 ipa_tz_unlock_reg_array_4_5[] = {
		0x04043583c, 0x00001000
		};

		static u32 ipa_tz_unlock_reg_array_3_5_1[] = {
		static u32 ipa_throughput_thresh_array_4_5[] = {
		310, 600, 1000
		};

		static u32 ipa_tz_unlock_reg_array_4_0[] = {
		0x04043583c, 0x00001000
		};

		static u32 ipa_ram_mmap_array_4_0[] = {
		0x00000280, 0x00000000, 0x00000000, 0x00000288, 0x00000078,
		0x00004000, 0x00000308, 0x00000078, 0x00004000, 0x00000388,
		0x00000078, 0x00004000, 0x00000408, 0x00000078, 0x00004000,
		0x0000000F, 0x00000000, 0x00000007, 0x00000008, 0x0000000E,
		0x00000488, 0x00000078, 0x00004000, 0x00000508, 0x00000078,
		0x00004000, 0x0000000F, 0x00000000, 0x00000007, 0x00000008,
		0x0000000E, 0x00000588, 0x00000078, 0x00004000, 0x00000608,
		0x00000078, 0x00004000, 0x00000688, 0x00000140, 0x000007C8,
		0x00000000, 0x00000800, 0x000007D0, 0x00000200, 0x000009D0,
		0x00000200, 0x00000000, 0x00000000, 0x00000000, 0x000013F0,
		0x0000100C, 0x000023FC, 0x00000000, 0x000023FC, 0x00000000,
		0x000023FC, 0x00000000, 0x000023FC, 0x00000000, 0x00000080,
		0x00000200, 0x00002800, 0x000023FC, 0x00000000, 0x000023FC,
		0x00000000, 0x000023FC, 0x00000000, 0x000023FC, 0x00000000,
		0x00002400, 0x00000400, 0x00000BD8, 0x00000050, 0x00000C30,
		0x00000060, 0x00000C90, 0x00000140, 0x00000DD0, 0x00000180,
		0x00000F50, 0x00000180, 0x000010D0, 0x00000180, 0x00001250,
		0x00000180, 0x000013D0, 0x00000020
		static u32 ipa_tz_unlock_reg_array_3_5_1[] = {
		0x04043583c, 0x00001000
		};

		static u32 ipa_ram_mmap_array_3_5_1[] = {
		0x00000280, 0x00000000, 0x00000000, 0x00000288, 0x00000078,
		0x00004000, 0x00000308, 0x00000078, 0x00004000, 0x00000388,
		0x00000078, 0x00004000, 0x00000408, 0x00000078, 0x00004000,
		0x0000000F, 0x00000000, 0x00000007, 0x00000008, 0x0000000E,
		0x00000488, 0x00000078, 0x00004000, 0x00000508, 0x00000078,
		0x00004000, 0x0000000F, 0x00000000, 0x00000007, 0x00000008,
		0x0000000E, 0x00000588, 0x00000078, 0x00004000, 0x00000608,
		0x00000078, 0x00004000, 0x00000688, 0x00000140, 0x000007C8,
		0x00000000, 0x00000800, 0x000007D0, 0x00000200, 0x000009D0,
		0x00000200, 0x00000000, 0x00000000, 0x00000000, 0x00000BD8,
		0x00001024, 0x00002000, 0x00000000, 0x00002000, 0x00000000,
		0x00002000, 0x00000000, 0x00002000, 0x00000000, 0x00000080,
		0x00000200, 0x00002000, 0x00002000, 0x00000000, 0x00002000,
		0x00000000, 0x00002000, 0x00000000, 0x00002000, 0x00000000,
		0x00001C00, 0x00000400
		struct dtsi_replacement_u32_array ipa3_plat_drv_u32_array_4_5[] = {
		{"qcom,mhi-event-ring-id-limits",
		mhi_event_ring_id_limits_array_4_5,
		ARRAY_SIZE(mhi_event_ring_id_limits_array_4_5) },
		{"qcom,ipa-tz-unlock-reg",
		ipa_tz_unlock_reg_array_4_5,
		ARRAY_SIZE(ipa_tz_unlock_reg_array_4_5) },
		{"qcom,throughput-threshold",
		ipa_throughput_thresh_array_4_5,
		ARRAY_SIZE(ipa_throughput_thresh_array_4_5) },
		};

		struct dtsi_replacement_u32_array ipa3_plat_drv_u32_array_4_0[] = {
		@@ -192,9 +208,6 @@ struct dtsi_replacement_u32_array ipa3_plat_drv_u32_array_4_0[] = {
		{"qcom,ipa-tz-unlock-reg",
		ipa_tz_unlock_reg_array_4_0,
		ARRAY_SIZE(ipa_tz_unlock_reg_array_4_0) },
		{"qcom,ipa-ram-mmap",
		ipa_ram_mmap_array_4_0,
		ARRAY_SIZE(ipa_ram_mmap_array_4_0) },
		};

		struct dtsi_replacement_u32_array ipa3_plat_drv_u32_array_3_5_1[] = {
		@@ -204,9 +217,6 @@ struct dtsi_replacement_u32_array ipa3_plat_drv_u32_array_3_5_1[] = {
		{"qcom,ipa-tz-unlock-reg",
		ipa_tz_unlock_reg_array_3_5_1,
		ARRAY_SIZE(ipa_tz_unlock_reg_array_3_5_1) },
		{"qcom,ipa-ram-mmap",
		ipa_ram_mmap_array_3_5_1,
		ARRAY_SIZE(ipa_ram_mmap_array_3_5_1) },
		};

		struct dtsi_replacement_u32_array_table
		@@ -215,11 +225,99 @@ ipa3_plat_drv_u32_array_table[] = {
		ARRAY_SIZE(ipa3_plat_drv_u32_array_3_5_1) },
		{ ipa3_plat_drv_u32_array_4_0,
		ARRAY_SIZE(ipa3_plat_drv_u32_array_4_0) },
		{ ipa3_plat_drv_u32_array_4_5,
		ARRAY_SIZE(ipa3_plat_drv_u32_array_4_5) },
		};

		#define INTCTRL_OFFSET 0x083C0000
		#define INTCTRL_SIZE 0x00000110

		#define IPA_BASE_OFFSET_4_5 0x01e00000
		#define IPA_BASE_SIZE_4_5 0x000c0000
		#define GSI_BASE_OFFSET_4_5 0x01e04000
		#define GSI_BASE_SIZE_4_5 0x00023000

		struct resource ipa3_plat_drv_resource_4_5[] = {
		/*
		* PLEASE NOTE: The following offset values below ("ipa-base",
		* "gsi-base", and "intctrl-base") are used to calculate
		* offsets relative to the PCI BAR0 address provided by the
		* PCI probe. After their use to calculate the offsets, they
		* are not used again, since PCI ultimately dictates where
		* things live.
		*/
		{
		IPA_BASE_OFFSET_4_5,
		(IPA_BASE_OFFSET_4_5 + IPA_BASE_SIZE_4_5),
		"ipa-base",
		IORESOURCE_MEM,
		0,
		NULL,
		NULL,
		NULL
		},

		{
		GSI_BASE_OFFSET_4_5,
		(GSI_BASE_OFFSET_4_5 + GSI_BASE_SIZE_4_5),
		"gsi-base",
		IORESOURCE_MEM,
		0,
		NULL,
		NULL,
		NULL
		},

		/*
		* The following entry is germane only to the emulator
		* environment. It is needed to locate the emulator's PCI
		* interrupt controller...
		*/
		{
		INTCTRL_OFFSET,
		(INTCTRL_OFFSET + INTCTRL_SIZE),
		"intctrl-base",
		IORESOURCE_MEM,
		0,
		NULL,
		NULL,
		NULL
		},

		{
		IPA_PIPE_MEM_START_OFST,
		(IPA_PIPE_MEM_START_OFST + IPA_PIPE_MEM_SIZE),
		"ipa-pipe-mem",
		IORESOURCE_MEM,
		0,
		NULL,
		NULL,
		NULL
		},

		{
		0,
		0,
		"gsi-irq",
		IORESOURCE_IRQ,
		0,
		NULL,
		NULL,
		NULL
		},

		{
		0,
		0,
		"ipa-irq",
		IORESOURCE_IRQ,
		0,
		NULL,
		NULL,
		NULL
		},
		};

		#define IPA_BASE_OFFSET_4_0 0x01e00000
		#define IPA_BASE_SIZE_4_0 0x00034000
		#define GSI_BASE_OFFSET_4_0 0x01e04000
		@@ -227,12 +325,12 @@ ipa3_plat_drv_u32_array_table[] = {

		struct resource ipa3_plat_drv_resource_4_0[] = {
		/*
		* PLEASE NOTE WELL: The following offset values below
		* ("ipa-base", "gsi-base", and "intctrl-base") are used to
		* calculate offsets relative to the PCI BAR0 address provided
		* by the PCI probe. After their use to calculate the
		* offsets, they are not used again, since PCI ultimately
		* dictates where things live.
		* PLEASE NOTE: The following offset values below ("ipa-base",
		* "gsi-base", and "intctrl-base") are used to calculate
		* offsets relative to the PCI BAR0 address provided by the
		* PCI probe. After their use to calculate the offsets, they
		* are not used again, since PCI ultimately dictates where
		* things live.
		*/
		{
		IPA_BASE_OFFSET_4_0,
		@@ -313,12 +411,12 @@ struct resource ipa3_plat_drv_resource_4_0[] = {

		struct resource ipa3_plat_drv_resource_3_5_1[] = {
		/*
		* PLEASE NOTE WELL: The following offset values below
		* ("ipa-base", "gsi-base", and "intctrl-base") are used to
		* calculate offsets relative to the PCI BAR0 address provided
		* by the PCI probe. After their use to calculate the
		* offsets, they are not used again, since PCI ultimately
		* dictates where things live.
		* PLEASE NOTE: The following offset values below ("ipa-base",
		* "gsi-base", and "intctrl-base") are used to calculate
		* offsets relative to the PCI BAR0 address provided by the
		* PCI probe. After their use to calculate the offsets, they
		* are not used again, since PCI ultimately dictates where
		* things live.
		*/
		{
		IPA_BASE_OFFSET_3_5_1,
		@@ -398,6 +496,8 @@ ipa3_plat_drv_resource_table[] = {
		ARRAY_SIZE(ipa3_plat_drv_resource_3_5_1) },
		{ ipa3_plat_drv_resource_4_0,
		ARRAY_SIZE(ipa3_plat_drv_resource_4_0) },
		{ ipa3_plat_drv_resource_4_5,
		ARRAY_SIZE(ipa3_plat_drv_resource_4_5) },
		};

		/*
		@@ -420,6 +520,9 @@ static u32 emulator_type_to_index(void)
		case IPA_HW_v4_0:
		index = DTSI_INDEX_4_0;
		break;
		case IPA_HW_v4_5:
		index = DTSI_INDEX_4_5;
		break;
		default:
		break;
		}

drivers/platform/msm/ipa/ipa_v3/ipa_i.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -286,6 +286,7 @@ enum {
		*/
		#define IPA_FWS_PATH_4_0 "ipa/4.0/ipa_fws.elf"
		#define IPA_FWS_PATH_3_5_1 "ipa/3.5.1/ipa_fws.elf"
		#define IPA_FWS_PATH_4_5 "ipa/4.5/ipa_fws.elf"

		#ifdef CONFIG_COMPAT
		#define IPA_IOC_ADD_HDR32 _IOWR(IPA_IOC_MAGIC, \

drivers/platform/msm/ipa/ipa_v3/ipa_utils.c

+120 −80

File changed.

Preview size limit exceeded, changes collapsed.