Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 1afe0952 authored by Govinda Rajulu Chenna's avatar Govinda Rajulu Chenna
Browse files

drm/msm: update intf timing and flush cfg for dsc-over-dp 



Update DP interface timing engine configurations as per
hw programming requirements for dsc-over-dp usecases.

Change-Id: Ibb18b71340cbd71e87c5caef11c9c29804911ac2
Signed-off-by: default avatarGovinda Rajulu Chenna <gchenna@codeaurora.org>
parent 2e4e6c46

drivers/gpu/drm/msm/msm_drv.h

+3 −0
Original line number Diff line number Diff line
@@ -341,6 +341,7 @@ struct msm_roi_caps { 
 * @range_min_qp:            Min QP allowed.

 * @range_max_qp:            Max QP allowed.

 * @range_bpg_offset:        Bits per group adjustment.

 * @extra_width:             Extra width required in timing calculations

 */

struct msm_display_dsc_info {

	u8 version;
@@ -396,6 +397,8 @@ struct msm_display_dsc_info { 
	char *range_min_qp;

	char *range_max_qp;

	char *range_bpg_offset;



	u32 extra_width;

};



/**

drivers/gpu/drm/msm/sde/sde_encoder.c

+19 −0
Original line number Diff line number Diff line
@@ -3104,6 +3104,14 @@ static void sde_encoder_virt_enable(struct drm_encoder *drm_enc) 
		phys->comp_type = comp_info->comp_type;

		phys->comp_ratio = comp_info->comp_ratio;

		phys->wide_bus_en = mode_info.wide_bus_en;



		if (phys->comp_type == MSM_DISPLAY_COMPRESSION_DSC) {

			phys->dsc_extra_pclk_cycle_cnt =

				comp_info->dsc_info.pclk_per_line;

			phys->dsc_extra_disp_width =

				comp_info->dsc_info.extra_width;

		}



		if (phys != sde_enc->cur_master) {

			/**

			 * on DMS request, the encoder will be enabled
@@ -3518,6 +3526,7 @@ static inline void _sde_encoder_trigger_flush(struct drm_encoder *drm_enc, 
	unsigned long lock_flags;

	struct sde_encoder_virt *sde_enc;

	int pend_ret_fence_cnt;

	struct sde_connector *c_conn;



	if (!drm_enc || !phys) {

		SDE_ERROR("invalid argument(s), drm_enc %d, phys_enc %d\n",
@@ -3526,6 +3535,7 @@ static inline void _sde_encoder_trigger_flush(struct drm_encoder *drm_enc, 
	}



	sde_enc = to_sde_encoder_virt(drm_enc);

	c_conn = to_sde_connector(phys->connector);



	if (!phys->hw_pp) {

		SDE_ERROR("invalid pingpong hw\n");
@@ -3554,6 +3564,15 @@ static inline void _sde_encoder_trigger_flush(struct drm_encoder *drm_enc, 


	pend_ret_fence_cnt = atomic_read(&phys->pending_retire_fence_cnt);



	/* perform peripheral flush on every frame update for dp dsc */

	if (phys->hw_intf && phys->hw_intf->cap->type == INTF_DP &&

			phys->comp_type == MSM_DISPLAY_COMPRESSION_DSC &&

			phys->comp_ratio && ctl->ops.update_bitmask_periph &&

			c_conn->ops.update_pps) {

		c_conn->ops.update_pps(phys->connector, NULL, c_conn->display);

		ctl->ops.update_bitmask_periph(ctl, phys->hw_intf->idx, 1);

	}



	if ((extra_flush && extra_flush->pending_flush_mask)

			&& ctl->ops.update_pending_flush)

		ctl->ops.update_pending_flush(ctl, extra_flush);

drivers/gpu/drm/msm/sde/sde_encoder_phys.h

+4 −0
Original line number Diff line number Diff line
@@ -267,6 +267,8 @@ struct sde_encoder_irq { 
 *                      path supports SDE_CTL_ACTIVE_CFG

 * @comp_type:      Type of compression supported

 * @comp_ratio:		Compression ratio

 * @dsc_extra_pclk_cycle_cnt: Extra pclk cycle count for DSC over DP

 * @dsc_extra_disp_width: Additional display width for DSC over DP

 * @wide_bus_en:	Wide-bus configuraiton

 * @enc_spinlock:	Virtual-Encoder-Wide Spin Lock for IRQ purposes

 * @enable_state:	Enable state tracking
@@ -311,6 +313,8 @@ struct sde_encoder_phys { 
	struct sde_hw_intf_cfg_v1 intf_cfg_v1;

	enum msm_display_compression_type comp_type;

	enum msm_display_compression_ratio comp_ratio;

	u32 dsc_extra_pclk_cycle_cnt;

	u32 dsc_extra_disp_width;

	bool wide_bus_en;

	spinlock_t *enc_spinlock;

	enum sde_enc_enable_state enable_state;

drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c

+11 −0
Original line number Diff line number Diff line
@@ -113,6 +113,7 @@ static void drm_mode_to_intf_timing_params( 
	timing->underflow_clr = 0xff;

	timing->hsync_skew = mode->hskew;

	timing->v_front_porch_fixed = vid_enc->base.vfp_cached;

	timing->compression_en = false;



	/* DSI controller cannot handle active-low sync signals. */

	if (phys_enc->hw_intf->cap->type == INTF_DSI) {
@@ -143,6 +144,16 @@ static void drm_mode_to_intf_timing_params( 
		timing->h_back_porch = timing->h_back_porch >> 1;

		timing->h_front_porch = timing->h_front_porch >> 1;

		timing->hsync_pulse_width = timing->hsync_pulse_width >> 1;



		if (vid_enc->base.comp_type == MSM_DISPLAY_COMPRESSION_DSC &&

				vid_enc->base.comp_ratio) {

			timing->compression_en = true;

			timing->extra_dto_cycles =

				vid_enc->base.dsc_extra_pclk_cycle_cnt;

			timing->width += vid_enc->base.dsc_extra_disp_width;

			timing->h_back_porch +=

				vid_enc->base.dsc_extra_disp_width;

		}

	}



	/*

drivers/gpu/drm/msm/sde/sde_hw_intf.c

+30 −6
Original line number Diff line number Diff line
@@ -198,6 +198,8 @@ static void sde_hw_intf_setup_timing_engine(struct sde_hw_intf *ctx, 
	u32 polarity_ctl, den_polarity, hsync_polarity, vsync_polarity;

	u32 panel_format;

	u32 intf_cfg, intf_cfg2;

	u32 display_data_hctl = 0, active_data_hctl = 0;

	bool dp_intf = false;



	/* read interface_cfg */

	intf_cfg = SDE_REG_READ(c, INTF_CONFIG);
@@ -211,14 +213,12 @@ static void sde_hw_intf_setup_timing_engine(struct sde_hw_intf *ctx, 
	display_v_end = ((vsync_period - p->v_front_porch) * hsync_period) +

	p->hsync_skew - 1;



	if (ctx->cap->type == INTF_EDP || ctx->cap->type == INTF_DP) {

		display_v_start += p->hsync_pulse_width + p->h_back_porch;

		display_v_end -= p->h_front_porch;

	}



	hsync_start_x = p->h_back_porch + p->hsync_pulse_width;

	hsync_end_x = hsync_period - p->h_front_porch - 1;



	if (ctx->cap->type == INTF_EDP || ctx->cap->type == INTF_DP)

		dp_intf = true;



	if (p->width != p->xres) {

		active_h_start = hsync_start_x;

		active_h_end = active_h_start + p->xres - 1;
@@ -248,6 +248,29 @@ static void sde_hw_intf_setup_timing_engine(struct sde_hw_intf *ctx, 
	hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width;

	display_hctl = (hsync_end_x << 16) | hsync_start_x;



	if (dp_intf) {

		active_h_start = hsync_start_x;

		active_h_end = active_h_start + p->xres - 1;

		active_v_start = display_v_start;

		active_v_end = active_v_start + (p->yres * hsync_period) - 1;



		display_v_start += p->hsync_pulse_width + p->h_back_porch;



		active_hctl = (active_h_end << 16) | active_h_start;

		display_hctl = active_hctl;

	}



	intf_cfg2 = 0;



	if (dp_intf && p->compression_en) {

		active_data_hctl = (hsync_start_x + p->extra_dto_cycles) << 16;

		active_data_hctl += hsync_start_x;



		display_data_hctl = active_data_hctl;



		intf_cfg2 |= BIT(4);

	}



	den_polarity = 0;

	if (ctx->cap->type == INTF_HDMI) {

		hsync_polarity = p->yres >= 720 ? 0 : 1;
@@ -272,7 +295,6 @@ static void sde_hw_intf_setup_timing_engine(struct sde_hw_intf *ctx, 
				(COLOR_8BIT << 4) |

				(0x21 << 8));



	intf_cfg2 = 0;

	if (p->wide_bus_en)

		intf_cfg2 |= BIT(0);
@@ -294,6 +316,8 @@ static void sde_hw_intf_setup_timing_engine(struct sde_hw_intf *ctx, 
	SDE_REG_WRITE(c, INTF_CONFIG, intf_cfg);

	SDE_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format);

	SDE_REG_WRITE(c, INTF_CONFIG2, intf_cfg2);

	SDE_REG_WRITE(c, INTF_DISPLAY_DATA_HCTL, display_data_hctl);

	SDE_REG_WRITE(c, INTF_ACTIVE_DATA_HCTL, active_data_hctl);

}



static void sde_hw_intf_enable_timing_engine(