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Commit 19f5a775 authored by Rama Krishna Phani A's avatar Rama Krishna Phani A
Browse files

msm: ep_pcie: Update enablement for TCSR PERST



Few targets does not support TCSR PCIe perst.
Enable perst programming only for supported targets.

Change-Id: I954ea5caef2b13748e5b9137aa9dfcaebd577847
Signed-off-by: default avatarRama Krishna Phani A <rphani@codeaurora.org>
parent fff51c15
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+1 −0
Original line number Diff line number Diff line
@@ -61,6 +61,7 @@ Optional Properties:
  - qcom,pcie-mhi-a7-irq: boolean type; MHI a7 has separate irq.
  - qcom,pcie-perst-enum: Link enumeration will be triggered by PERST
    deassertion.
  - qcom,tcsr-not-supported: TCSR pcie perst is not supported.
  - mdm2apstatus-gpio: GPIO used by PCIe endpoint side to notify the host side.
  - Refer to "Documentation/devicetree/bindings/arm/msm/msm_bus.txt" for
    below optional properties:
+1 −0
Original line number Diff line number Diff line
@@ -344,6 +344,7 @@ struct ep_pcie_dev_t {
	bool                         aggregated_irq;
	bool                         mhi_a7_irq;
	bool                         pcie_edma;
	bool                         tcsr_not_supported;
	u32                          dbi_base_reg;
	u32                          slv_space_reg;
	u32                          phy_status_reg;
+60 −40
Original line number Diff line number Diff line
@@ -1014,6 +1014,7 @@ static int ep_pcie_get_resources(struct ep_pcie_dev_t *dev,
	char prop_name[MAX_PROP_SIZE];
	const __be32 *prop;
	u32 *clkfreq = NULL;
	bool map;

	EP_PCIE_DBG(dev, "PCIe V%d\n", dev->rev);

@@ -1230,6 +1231,7 @@ static int ep_pcie_get_resources(struct ep_pcie_dev_t *dev,

	for (i = 0; i < EP_PCIE_MAX_RES; i++) {
		res_info = &dev->res[i];
		map = false;

		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
							res_info->name);
@@ -1238,13 +1240,19 @@ static int ep_pcie_get_resources(struct ep_pcie_dev_t *dev,
			EP_PCIE_ERR(dev,
				"PCIe V%d: can't get resource for %s\n",
					dev->rev, res_info->name);
			if (!strcmp(res_info->name, "tcsr_pcie_perst_en")) {
				if (!dev->tcsr_not_supported) {
					ret = -ENOMEM;
					goto out;
				}
			}
		} else {
			EP_PCIE_DBG(dev, "start addr for %s is %pa\n",
				res_info->name,	&res->start);
			map = true;
		}

		if (map) {
			res_info->base = devm_ioremap(&pdev->dev,
					res->start, resource_size(res));
			if (!res_info->base) {
@@ -1255,6 +1263,7 @@ static int ep_pcie_get_resources(struct ep_pcie_dev_t *dev,
			}
			res_info->resource = res;
		}
	}

	for (i = 0; i < EP_PCIE_MAX_IRQ; i++) {
		irq_info = &dev->irq[i];
@@ -1403,6 +1412,7 @@ int ep_pcie_core_enable_endpoint(enum ep_pcie_options opt)

		dev->power_on = true;

		if (!dev->tcsr_not_supported) {
			EP_PCIE_DBG(dev,
				"TCSR PERST_EN value before configure:0x%x\n",
				readl_relaxed(dev->tcsr_perst_en + 0x258));
@@ -1423,6 +1433,7 @@ int ep_pcie_core_enable_endpoint(enum ep_pcie_options opt)
			 */
			writel_relaxed(0, dev->tcsr_perst_en +
						TCSR_PERST_SEPARATION_ENABLE);
		}

		 /* check link status during initial bootup */
		if (!dev->enumerated) {
@@ -1476,6 +1487,7 @@ int ep_pcie_core_enable_endpoint(enum ep_pcie_options opt)
	if (!(opt & EP_PCIE_OPT_ENUM))
		goto out;

	if (!dev->tcsr_not_supported) {
		EP_PCIE_DBG(dev,
			"TCSR PERST_EN value before configure:0x%x\n",
			readl_relaxed(dev->tcsr_perst_en + 0x258));
@@ -1489,6 +1501,7 @@ int ep_pcie_core_enable_endpoint(enum ep_pcie_options opt)
		EP_PCIE_DBG(dev,
			"TCSR PERST_EN value after configure:0x%x\n",
			readl_relaxed(dev->tcsr_perst_en));
	}

	if (opt & EP_PCIE_OPT_AST_WAKE) {
		/* assert PCIe WAKE# */
@@ -2748,6 +2761,13 @@ static int ep_pcie_probe(struct platform_device *pdev)
		"PCIe V%d: enum by PERST is %s enabled\n",
		ep_pcie_dev.rev, ep_pcie_dev.perst_enum ? "" : "not");

	ep_pcie_dev.tcsr_not_supported = of_property_read_bool
		((&pdev->dev)->of_node,
				"qcom,tcsr-not-supported");
	EP_PCIE_DBG(&ep_pcie_dev,
		"PCIe V%d: tcsr pcie perst is %s supported\n",
		ep_pcie_dev.rev, ep_pcie_dev.tcsr_not_supported ? "not" : "");

	ep_pcie_dev.rev = 1711211;
	ep_pcie_dev.pdev = pdev;
	memcpy(ep_pcie_dev.vreg, ep_pcie_vreg_info,