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Commit 19d4365e authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "drm/msm/sde: Expand sspp lut_dma buf for multi-rect use cases" into dev/msm-4.14-display

parents 77e06261 f1e039cc

drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.c

+89 −65
Original line number Diff line number Diff line
@@ -92,7 +92,8 @@ 
#define QSEED3_COEF_LUT_CTRL_OFF               0x4C



static struct sde_reg_dma_buffer *dspp_buf[REG_DMA_FEATURES_MAX][DSPP_MAX];

static struct sde_reg_dma_buffer *sspp_buf[REG_DMA_FEATURES_MAX][SSPP_MAX];

static struct sde_reg_dma_buffer

	*sspp_buf[SDE_SSPP_RECT_MAX][REG_DMA_FEATURES_MAX][SSPP_MAX];



static u32 feature_map[SDE_DSPP_MAX] = {

	[SDE_DSPP_VLUT] = VLUT,
@@ -189,7 +190,8 @@ static int reg_dma_buf_init(struct sde_reg_dma_buffer **buf, u32 sz); 
static int reg_dma_dspp_check(struct sde_hw_dspp *ctx, void *cfg,

		enum sde_reg_dma_features feature);

static int reg_dma_sspp_check(struct sde_hw_pipe *ctx, void *cfg,

		enum sde_reg_dma_features feature);

		enum sde_reg_dma_features feature,

		enum sde_sspp_multirect_index idx);



static int reg_dma_buf_init(struct sde_reg_dma_buffer **buf, u32 size)

{
@@ -1576,7 +1578,7 @@ int reg_dmav1_init_sspp_op_v4(int feature, enum sde_sspp idx) 
	int rc = -ENOTSUPP;

	struct sde_hw_reg_dma_ops *dma_ops;

	bool is_supported = false;

	u32 blk;

	u32 blk, i = 0;



	if (feature >= SDE_SSPP_MAX || idx >= SSPP_MAX) {

		DRM_ERROR("invalid feature %x max %x sspp idx %x max %xd\n",
@@ -1600,15 +1602,25 @@ int reg_dmav1_init_sspp_op_v4(int feature, enum sde_sspp idx) 
	if (!rc)

		rc = (is_supported) ? 0 : -ENOTSUPP;



	if (!rc)

		rc = reg_dma_buf_init(&sspp_buf[sspp_feature_map[feature]][idx],

	if (!rc) {

		for (i = SDE_SSPP_RECT_0; i < SDE_SSPP_RECT_MAX; i++) {

			rc = reg_dma_buf_init(

				&sspp_buf[i][sspp_feature_map[feature]][idx],

				sspp_feature_reg_dma_sz[feature]);

			if (rc) {

				DRM_ERROR("rect %d buf init failed\n", i);

				break;

			}

		}



	}



	return rc;

}



static int reg_dma_sspp_check(struct sde_hw_pipe *ctx, void *cfg,

		enum sde_reg_dma_features feature)

		enum sde_reg_dma_features feature,

		enum sde_sspp_multirect_index idx)

{

	struct sde_hw_reg_dma_ops *dma_ops;

	struct sde_hw_cp_cfg *hw_cfg = cfg;
@@ -1618,6 +1630,11 @@ static int reg_dma_sspp_check(struct sde_hw_pipe *ctx, void *cfg, 
		return -EINVAL;

	}



	if (idx >= SDE_SSPP_RECT_MAX) {

		DRM_ERROR("invalid multirect idx %d\n", idx);

		return -EINVAL;

	}



	dma_ops = sde_reg_dma_get_ops();

	if (IS_ERR_OR_NULL(dma_ops))

		return -EINVAL;
@@ -1629,8 +1646,9 @@ static int reg_dma_sspp_check(struct sde_hw_pipe *ctx, void *cfg, 
		return -EINVAL;

	}



	if (!sspp_buf[feature][ctx->idx]) {

		DRM_ERROR("invalid dma_buf for sspp idx %d\n", ctx->idx);

	if (!sspp_buf[idx][feature][ctx->idx]) {

		DRM_ERROR("invalid dma_buf for rect idx %d sspp idx %d\n", idx,

			ctx->idx);

		return -EINVAL;

	}
@@ -1646,12 +1664,13 @@ static void vig_gamutv5_off(struct sde_hw_pipe *ctx, void *cfg) 
	struct sde_reg_dma_setup_ops_cfg dma_write_cfg;

	struct sde_reg_dma_kickoff_cfg kick_off;

	u32 gamut_base = ctx->cap->sblk->gamut_blk.base - REG_DMA_VIG_SWI_DIFF;

	enum sde_sspp_multirect_index idx = SDE_SSPP_RECT_0;



	dma_ops = sde_reg_dma_get_ops();

	dma_ops->reset_reg_dma_buf(sspp_buf[GAMUT][ctx->idx]);

	dma_ops->reset_reg_dma_buf(sspp_buf[idx][GAMUT][ctx->idx]);



	REG_DMA_INIT_OPS(dma_write_cfg, sspp_mapping[ctx->idx], GAMUT,

			sspp_buf[GAMUT][ctx->idx]);

			sspp_buf[idx][GAMUT][ctx->idx]);



	REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0, 0);

	rc = dma_ops->setup_payload(&dma_write_cfg);
@@ -1669,8 +1688,9 @@ static void vig_gamutv5_off(struct sde_hw_pipe *ctx, void *cfg) 
		return;

	}



	REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl, sspp_buf[GAMUT][ctx->idx],

			REG_DMA_WRITE, DMA_CTL_QUEUE0, WRITE_IMMEDIATE);

	REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl,

			sspp_buf[idx][GAMUT][ctx->idx], REG_DMA_WRITE,

			DMA_CTL_QUEUE0, WRITE_IMMEDIATE);

	rc = dma_ops->kick_off(&kick_off);

	if (rc)

		DRM_ERROR("failed to kick off ret %d\n", rc);
@@ -1688,8 +1708,9 @@ void reg_dmav1_setup_vig_gamutv5(struct sde_hw_pipe *ctx, void *cfg) 
	struct sde_reg_dma_kickoff_cfg kick_off;

	u32 gamut_base = ctx->cap->sblk->gamut_blk.base - REG_DMA_VIG_SWI_DIFF;

	bool use_2nd_memory = false;

	enum sde_sspp_multirect_index idx = SDE_SSPP_RECT_0;



	rc = reg_dma_sspp_check(ctx, cfg, GAMUT);

	rc = reg_dma_sspp_check(ctx, cfg, GAMUT, idx);

	if (rc)

		return;
@@ -1714,10 +1735,10 @@ void reg_dmav1_setup_vig_gamutv5(struct sde_hw_pipe *ctx, void *cfg) 
	}



	dma_ops = sde_reg_dma_get_ops();

	dma_ops->reset_reg_dma_buf(sspp_buf[GAMUT][ctx->idx]);

	dma_ops->reset_reg_dma_buf(sspp_buf[idx][GAMUT][ctx->idx]);



	REG_DMA_INIT_OPS(dma_write_cfg, sspp_mapping[ctx->idx], GAMUT,

			sspp_buf[GAMUT][ctx->idx]);

			sspp_buf[idx][GAMUT][ctx->idx]);



	REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0, 0);

	rc = dma_ops->setup_payload(&dma_write_cfg);
@@ -1778,8 +1799,9 @@ void reg_dmav1_setup_vig_gamutv5(struct sde_hw_pipe *ctx, void *cfg) 
		return;

	}



	REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl, sspp_buf[GAMUT][ctx->idx],

			REG_DMA_WRITE, DMA_CTL_QUEUE0, WRITE_IMMEDIATE);

	REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl,

			sspp_buf[idx][GAMUT][ctx->idx], REG_DMA_WRITE,

			DMA_CTL_QUEUE0, WRITE_IMMEDIATE);

	rc = dma_ops->kick_off(&kick_off);

	if (rc)

		DRM_ERROR("failed to kick off ret %d\n", rc);
@@ -1794,12 +1816,13 @@ static void vig_igcv5_off(struct sde_hw_pipe *ctx, void *cfg) 
	struct sde_reg_dma_setup_ops_cfg dma_write_cfg;

	struct sde_reg_dma_kickoff_cfg kick_off;

	u32 igc_base = ctx->cap->sblk->igc_blk[0].base - REG_DMA_VIG_SWI_DIFF;

	enum sde_sspp_multirect_index idx = SDE_SSPP_RECT_0;



	dma_ops = sde_reg_dma_get_ops();

	dma_ops->reset_reg_dma_buf(sspp_buf[IGC][ctx->idx]);

	dma_ops->reset_reg_dma_buf(sspp_buf[idx][IGC][ctx->idx]);



	REG_DMA_INIT_OPS(dma_write_cfg, sspp_mapping[ctx->idx], IGC,

			sspp_buf[IGC][ctx->idx]);

			sspp_buf[idx][IGC][ctx->idx]);



	REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0, 0);

	rc = dma_ops->setup_payload(&dma_write_cfg);
@@ -1816,8 +1839,9 @@ static void vig_igcv5_off(struct sde_hw_pipe *ctx, void *cfg) 
		return;

	}



	REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl, sspp_buf[IGC][ctx->idx],

			REG_DMA_WRITE, DMA_CTL_QUEUE0, WRITE_IMMEDIATE);

	REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl,

			sspp_buf[idx][IGC][ctx->idx], REG_DMA_WRITE,

			DMA_CTL_QUEUE0, WRITE_IMMEDIATE);

	rc = dma_ops->kick_off(&kick_off);

	if (rc)

		DRM_ERROR("failed to kick off ret %d\n", rc);
@@ -1836,8 +1860,9 @@ void reg_dmav1_setup_vig_igcv5(struct sde_hw_pipe *ctx, void *cfg) 
	struct sde_reg_dma_setup_ops_cfg dma_write_cfg;

	struct sde_reg_dma_kickoff_cfg kick_off;

	u32 igc_base = ctx->cap->sblk->igc_blk[0].base - REG_DMA_VIG_SWI_DIFF;

	enum sde_sspp_multirect_index idx = SDE_SSPP_RECT_0;



	rc = reg_dma_sspp_check(ctx, cfg, IGC);

	rc = reg_dma_sspp_check(ctx, cfg, IGC, idx);

	if (rc)

		return;
@@ -1855,10 +1880,10 @@ void reg_dmav1_setup_vig_igcv5(struct sde_hw_pipe *ctx, void *cfg) 
	}



	dma_ops = sde_reg_dma_get_ops();

	dma_ops->reset_reg_dma_buf(sspp_buf[IGC][ctx->idx]);

	dma_ops->reset_reg_dma_buf(sspp_buf[idx][IGC][ctx->idx]);



	REG_DMA_INIT_OPS(dma_write_cfg, sspp_mapping[ctx->idx], IGC,

			sspp_buf[IGC][ctx->idx]);

			sspp_buf[idx][IGC][ctx->idx]);



	REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0, 0);

	rc = dma_ops->setup_payload(&dma_write_cfg);
@@ -1927,8 +1952,9 @@ void reg_dmav1_setup_vig_igcv5(struct sde_hw_pipe *ctx, void *cfg) 
		goto exit;

	}



	REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl, sspp_buf[IGC][ctx->idx],

			REG_DMA_WRITE, DMA_CTL_QUEUE0, WRITE_IMMEDIATE);

	REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl,

			sspp_buf[idx][IGC][ctx->idx], REG_DMA_WRITE,

			DMA_CTL_QUEUE0, WRITE_IMMEDIATE);

	rc = dma_ops->kick_off(&kick_off);

	if (rc)

		DRM_ERROR("failed to kick off ret %d\n", rc);
@@ -1948,10 +1974,10 @@ static void dma_igcv5_off(struct sde_hw_pipe *ctx, void *cfg, 
	u32 igc_opmode_off;



	dma_ops = sde_reg_dma_get_ops();

	dma_ops->reset_reg_dma_buf(sspp_buf[IGC][ctx->idx]);

	dma_ops->reset_reg_dma_buf(sspp_buf[idx][IGC][ctx->idx]);



	REG_DMA_INIT_OPS(dma_write_cfg, sspp_mapping[ctx->idx], IGC,

			sspp_buf[IGC][ctx->idx]);

			sspp_buf[idx][IGC][ctx->idx]);



	REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0, 0);

	rc = dma_ops->setup_payload(&dma_write_cfg);
@@ -1974,8 +2000,9 @@ static void dma_igcv5_off(struct sde_hw_pipe *ctx, void *cfg, 
		return;

	}



	REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl, sspp_buf[IGC][ctx->idx],

			REG_DMA_WRITE, DMA_CTL_QUEUE0, WRITE_IMMEDIATE);

	REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl,

			sspp_buf[idx][IGC][ctx->idx], REG_DMA_WRITE,

			DMA_CTL_QUEUE0, WRITE_IMMEDIATE);

	rc = dma_ops->kick_off(&kick_off);

	if (rc)

		DRM_ERROR("failed to kick off ret %d\n", rc);
@@ -1994,15 +2021,10 @@ void reg_dmav1_setup_dma_igcv5(struct sde_hw_pipe *ctx, void *cfg, 
	struct sde_reg_dma_kickoff_cfg kick_off;

	u32 igc_base, igc_dither_off, igc_opmode_off;



	rc = reg_dma_sspp_check(ctx, cfg, IGC);

	rc = reg_dma_sspp_check(ctx, cfg, IGC, idx);

	if (rc)

		return;



	if (idx > SDE_SSPP_RECT_1) {

		DRM_ERROR("invalid multirect idx %d\n", idx);

		return;

	}



	igc_lut = hw_cfg->payload;

	if (!igc_lut) {

		DRM_DEBUG_DRIVER("disable igc feature\n");
@@ -2017,10 +2039,10 @@ void reg_dmav1_setup_dma_igcv5(struct sde_hw_pipe *ctx, void *cfg, 
	}



	dma_ops = sde_reg_dma_get_ops();

	dma_ops->reset_reg_dma_buf(sspp_buf[IGC][ctx->idx]);

	dma_ops->reset_reg_dma_buf(sspp_buf[idx][IGC][ctx->idx]);



	REG_DMA_INIT_OPS(dma_write_cfg, sspp_mapping[ctx->idx], IGC,

			sspp_buf[IGC][ctx->idx]);

			sspp_buf[idx][IGC][ctx->idx]);



	REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0, 0);

	rc = dma_ops->setup_payload(&dma_write_cfg);
@@ -2082,8 +2104,9 @@ void reg_dmav1_setup_dma_igcv5(struct sde_hw_pipe *ctx, void *cfg, 
		goto igc_exit;

	}



	REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl, sspp_buf[IGC][ctx->idx],

			REG_DMA_WRITE, DMA_CTL_QUEUE0, WRITE_IMMEDIATE);

	REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl,

			sspp_buf[idx][IGC][ctx->idx], REG_DMA_WRITE,

			DMA_CTL_QUEUE0, WRITE_IMMEDIATE);

	rc = dma_ops->kick_off(&kick_off);

	if (rc)

		DRM_ERROR("failed to kick off ret %d\n", rc);
@@ -2103,10 +2126,10 @@ static void dma_gcv5_off(struct sde_hw_pipe *ctx, void *cfg, 
	u32 gc_opmode_off;



	dma_ops = sde_reg_dma_get_ops();

	dma_ops->reset_reg_dma_buf(sspp_buf[GC][ctx->idx]);

	dma_ops->reset_reg_dma_buf(sspp_buf[idx][GC][ctx->idx]);



	REG_DMA_INIT_OPS(dma_write_cfg, sspp_mapping[ctx->idx], GC,

			sspp_buf[GC][ctx->idx]);

			sspp_buf[idx][GC][ctx->idx]);



	REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0, 0);

	rc = dma_ops->setup_payload(&dma_write_cfg);
@@ -2129,8 +2152,9 @@ static void dma_gcv5_off(struct sde_hw_pipe *ctx, void *cfg, 
		return;

	}



	REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl, sspp_buf[GC][ctx->idx],

			REG_DMA_WRITE, DMA_CTL_QUEUE0, WRITE_IMMEDIATE);

	REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl,

			sspp_buf[idx][GC][ctx->idx], REG_DMA_WRITE,

			DMA_CTL_QUEUE0, WRITE_IMMEDIATE);

	rc = dma_ops->kick_off(&kick_off);

	if (rc)

		DRM_ERROR("failed to kick off ret %d\n", rc);
@@ -2149,15 +2173,10 @@ void reg_dmav1_setup_dma_gcv5(struct sde_hw_pipe *ctx, void *cfg, 
	struct sde_reg_dma_kickoff_cfg kick_off;

	u32 gc_base, gc_opmode_off;



	rc = reg_dma_sspp_check(ctx, cfg, GC);

	rc = reg_dma_sspp_check(ctx, cfg, GC, idx);

	if (rc)

		return;



	if (idx > SDE_SSPP_RECT_1) {

		DRM_ERROR("invalid multirect idx %d\n", idx);

		return;

	}



	gc_lut = hw_cfg->payload;

	if (!gc_lut) {

		DRM_DEBUG_DRIVER("disable gc feature\n");
@@ -2172,10 +2191,10 @@ void reg_dmav1_setup_dma_gcv5(struct sde_hw_pipe *ctx, void *cfg, 
	}



	dma_ops = sde_reg_dma_get_ops();

	dma_ops->reset_reg_dma_buf(sspp_buf[GC][ctx->idx]);

	dma_ops->reset_reg_dma_buf(sspp_buf[idx][GC][ctx->idx]);



	REG_DMA_INIT_OPS(dma_write_cfg, sspp_mapping[ctx->idx], GC,

			sspp_buf[GC][ctx->idx]);

			sspp_buf[idx][GC][ctx->idx]);



	REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0, 0);

	rc = dma_ops->setup_payload(&dma_write_cfg);
@@ -2219,8 +2238,9 @@ void reg_dmav1_setup_dma_gcv5(struct sde_hw_pipe *ctx, void *cfg, 
		goto gc_exit;

	}



	REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl, sspp_buf[GC][ctx->idx],

			REG_DMA_WRITE, DMA_CTL_QUEUE0, WRITE_IMMEDIATE);

	REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl,

			sspp_buf[idx][GC][ctx->idx], REG_DMA_WRITE,

			DMA_CTL_QUEUE0, WRITE_IMMEDIATE);

	rc = dma_ops->kick_off(&kick_off);

	if (rc)

		DRM_ERROR("failed to kick off ret %d\n", rc);
@@ -2230,7 +2250,7 @@ void reg_dmav1_setup_dma_gcv5(struct sde_hw_pipe *ctx, void *cfg, 


int reg_dmav1_deinit_sspp_ops(enum sde_sspp idx)

{

	int i;

	u32 i, j;

	struct sde_hw_reg_dma_ops *dma_ops;



	dma_ops = sde_reg_dma_get_ops();
@@ -2242,11 +2262,13 @@ int reg_dmav1_deinit_sspp_ops(enum sde_sspp idx) 
		return -EINVAL;

	}



	for (i = 0; i < REG_DMA_FEATURES_MAX; i++) {

		if (!sspp_buf[i][idx])

	for (i = SDE_SSPP_RECT_0; i < SDE_SSPP_RECT_MAX; i++) {

		for (j = 0; j < REG_DMA_FEATURES_MAX; j++) {

			if (!sspp_buf[i][j][idx])

				continue;

		dma_ops->dealloc_reg_dma(sspp_buf[i][idx]);

		sspp_buf[i][idx] = NULL;

			dma_ops->dealloc_reg_dma(sspp_buf[i][j][idx]);

			sspp_buf[i][j][idx] = NULL;

		}

	}

	return 0;

}
@@ -2392,6 +2414,7 @@ void reg_dmav1_setup_vig_qseed3(struct sde_hw_pipe *ctx, 
	u32 op_mode = 0, offset;

	u32 preload, src_y_rgb, src_uv, dst;

	u32 cache[4];

	enum sde_sspp_multirect_index idx = SDE_SSPP_RECT_0;



	if (!ctx || !pe || !scaler_cfg) {

		DRM_ERROR("invalid params ctx %pK pe %pK scaler_cfg %pK",
@@ -2402,7 +2425,7 @@ void reg_dmav1_setup_vig_qseed3(struct sde_hw_pipe *ctx, 
	hw_cfg.ctl = ctx->ctl;

	hw_cfg.payload = scaler_cfg;

	hw_cfg.len = sizeof(*scaler3_cfg);

	rc = reg_dma_sspp_check(ctx, &hw_cfg, QSEED);

	rc = reg_dma_sspp_check(ctx, &hw_cfg, QSEED, idx);

	if (rc || !sspp) {

		DRM_ERROR("invalid params rc %d sspp %pK\n", rc, sspp);

		return;
@@ -2410,10 +2433,10 @@ void reg_dmav1_setup_vig_qseed3(struct sde_hw_pipe *ctx, 


	offset = ctx->cap->sblk->scaler_blk.base - REG_DMA_VIG_SWI_DIFF;

	dma_ops = sde_reg_dma_get_ops();

	dma_ops->reset_reg_dma_buf(sspp_buf[QSEED][ctx->idx]);

	dma_ops->reset_reg_dma_buf(sspp_buf[idx][QSEED][ctx->idx]);



	REG_DMA_INIT_OPS(dma_write_cfg, sspp_mapping[ctx->idx], QSEED,

	    sspp_buf[QSEED][ctx->idx]);

	    sspp_buf[idx][QSEED][ctx->idx]);



	REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0, 0);

	rc = dma_ops->setup_payload(&dma_write_cfg);
@@ -2529,8 +2552,9 @@ void reg_dmav1_setup_vig_qseed3(struct sde_hw_pipe *ctx, 
		return;

	}



	REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg.ctl, sspp_buf[QSEED][ctx->idx],

			REG_DMA_WRITE, DMA_CTL_QUEUE0, WRITE_IMMEDIATE);

	REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg.ctl,

			sspp_buf[idx][QSEED][ctx->idx], REG_DMA_WRITE,

			DMA_CTL_QUEUE0, WRITE_IMMEDIATE);

	rc = dma_ops->kick_off(&kick_off);

	if (rc)

		DRM_ERROR("failed to kick off ret %d\n", rc);

drivers/gpu/drm/msm/sde/sde_hw_sspp.h

+2 −0
Original line number Diff line number Diff line
@@ -56,6 +56,7 @@ enum { 
 * SDE_SSPP_RECT_SOLO - multirect disabled

 * SDE_SSPP_RECT_0 - rect0 of a multirect pipe

 * SDE_SSPP_RECT_1 - rect1 of a multirect pipe

 * SDE_SSPP_RECT_MAX - max enum of multirect pipe

 *

 * Note: HW supports multirect with either RECT0 or

 * RECT1. Considering no benefit of such configs over
@@ -66,6 +67,7 @@ enum sde_sspp_multirect_index { 
	SDE_SSPP_RECT_SOLO = 0,

	SDE_SSPP_RECT_0,

	SDE_SSPP_RECT_1,

	SDE_SSPP_RECT_MAX,

};



enum sde_sspp_multirect_mode {