Loading arch/arm64/boot/dts/qcom/sdmmagpie-pinctrl.dtsi +43 −0 Original line number Diff line number Diff line Loading @@ -321,6 +321,49 @@ }; }; fpc_reset_int { fpc_reset_low: reset_low { mux { pins = "gpio91"; function = "fpc_reset_gpio_low"; }; config { pins = "gpio91"; drive-strength = <2>; bias-disable; output-low; }; }; fpc_reset_high: reset_high { mux { pins = "gpio91"; function = "fpc_reset_gpio_high"; }; config { pins = "gpio91"; drive-strength = <2>; bias-disable; output-high; }; }; fpc_int_low: int_low { mux { pins = "gpio90"; }; config { pins = "gpio90"; drive-strength = <2>; bias-pull-down; input-enable; }; }; }; /* SE 4 pin mappings */ qupv3_se4_i2c_pins: qupv3_se4_i2c_pins { qupv3_se4_i2c_active: qupv3_se4_i2c_active { Loading arch/arm64/boot/dts/qcom/sdmmagpie-qrd.dtsi +18 −0 Original line number Diff line number Diff line Loading @@ -17,7 +17,25 @@ #include "sdmmagpie-thermal-overlay.dtsi" #include "sdmmagpie-sde-display.dtsi" &soc { fpc1020 { compatible = "fpc,fpc1020"; interrupt-parent = <&tlmm>; interrupts = <90 0>; fpc,gpio_rst = <&tlmm 91 0x0>; fpc,gpio_irq = <&tlmm 90 0>; vcc_spi-supply = <&pm6150_l10>; vdd_io-supply = <&pm6150_l10>; vdd_ana-supply = <&pm6150_l10>; fpc,enable-on-boot; pinctrl-names = "fpc1020_reset_reset", "fpc1020_reset_active", "fpc1020_irq_active"; pinctrl-0 = <&fpc_reset_low>; pinctrl-1 = <&fpc_reset_high>; pinctrl-2 = <&fpc_int_low>; }; }; &qupv3_se7_i2c{ Loading Loading
arch/arm64/boot/dts/qcom/sdmmagpie-pinctrl.dtsi +43 −0 Original line number Diff line number Diff line Loading @@ -321,6 +321,49 @@ }; }; fpc_reset_int { fpc_reset_low: reset_low { mux { pins = "gpio91"; function = "fpc_reset_gpio_low"; }; config { pins = "gpio91"; drive-strength = <2>; bias-disable; output-low; }; }; fpc_reset_high: reset_high { mux { pins = "gpio91"; function = "fpc_reset_gpio_high"; }; config { pins = "gpio91"; drive-strength = <2>; bias-disable; output-high; }; }; fpc_int_low: int_low { mux { pins = "gpio90"; }; config { pins = "gpio90"; drive-strength = <2>; bias-pull-down; input-enable; }; }; }; /* SE 4 pin mappings */ qupv3_se4_i2c_pins: qupv3_se4_i2c_pins { qupv3_se4_i2c_active: qupv3_se4_i2c_active { Loading
arch/arm64/boot/dts/qcom/sdmmagpie-qrd.dtsi +18 −0 Original line number Diff line number Diff line Loading @@ -17,7 +17,25 @@ #include "sdmmagpie-thermal-overlay.dtsi" #include "sdmmagpie-sde-display.dtsi" &soc { fpc1020 { compatible = "fpc,fpc1020"; interrupt-parent = <&tlmm>; interrupts = <90 0>; fpc,gpio_rst = <&tlmm 91 0x0>; fpc,gpio_irq = <&tlmm 90 0>; vcc_spi-supply = <&pm6150_l10>; vdd_io-supply = <&pm6150_l10>; vdd_ana-supply = <&pm6150_l10>; fpc,enable-on-boot; pinctrl-names = "fpc1020_reset_reset", "fpc1020_reset_active", "fpc1020_irq_active"; pinctrl-0 = <&fpc_reset_low>; pinctrl-1 = <&fpc_reset_high>; pinctrl-2 = <&fpc_int_low>; }; }; &qupv3_se7_i2c{ Loading