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Commit 18924c71 authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu/gfx9: allow updating gfx mgpg state 



Wire up the functions to control medium grained
powergating.

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 197f95c8

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+50 −0
Original line number Diff line number Diff line
@@ -1992,6 +1992,34 @@ static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev, 
		data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));

}



void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,

						bool enable)

{

	uint32_t data, default_data;



	default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));

	if (enable == true)

		data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;

	else

		data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;

	if(default_data != data)

		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);

}



void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,

						bool enable)

{

	uint32_t data, default_data;



	default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));

	if (enable == true)

		data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;

	else

		data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;

	if(default_data != data)

		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);

}



static void gfx_v9_0_init_pg(struct amdgpu_device *adev)

{

	if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
@@ -3259,6 +3287,25 @@ static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev, 
	/* gfx_v9_0_exit_rlc_safe_mode(adev); */

}



static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,

						bool enable)

{

	/* TODO: double check if we need to perform under safe mode */

	/* gfx_v9_0_enter_rlc_safe_mode(adev); */



	if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)

		gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true);

	else

		gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false);



	if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)

		gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true);

	else

		gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false);



	/* gfx_v9_0_exit_rlc_safe_mode(adev); */

}



static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,

						      bool enable)

{
@@ -3469,6 +3516,9 @@ static int gfx_v9_0_set_powergating_state(void *handle, 


		/* update gfx cgpg state */

		gfx_v9_0_update_gfx_cg_power_gating(adev, enable);



		/* update mgcg state */

		gfx_v9_0_update_gfx_mg_power_gating(adev, enable);

		break;

	default:

		break;