Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 1865af21 authored by Yong Li's avatar Yong Li Committed by Linus Walleij
Browse files

pinctrl: aspeed: Fix ast2500 strap register write logic 



On AST2500, the hardware strap register(SCU70) only accepts write ‘1’,
to clear it to ‘0’, must set bits(write  ‘1’) to SCU7C

Signed-off-by: default avatarYong Li <sdliyong@gmail.com>
Reviewed-by: default avatarAndrew Jeffery <andrew@aj.id.au>
Tested-by: default avatarAndrew Jeffery <andrew@aj.id.au>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 1899ccc0

drivers/pinctrl/aspeed/pinctrl-aspeed.c

+17 −2
Original line number Diff line number Diff line
@@ -183,6 +183,7 @@ static int aspeed_sig_expr_set(const struct aspeed_sig_expr *expr, 
{

	int ret;

	int i;

	unsigned int rev_id;



	for (i = 0; i < expr->ndescs; i++) {

		const struct aspeed_sig_desc *desc = &expr->descs[i];
@@ -213,6 +214,20 @@ static int aspeed_sig_expr_set(const struct aspeed_sig_expr *expr, 
		if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP2)

			continue;



		/* On AST2500, Set bits in SCU7C are cleared from SCU70 */

		if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1) {

			ret = regmap_read(maps[ASPEED_IP_SCU],

				HW_REVISION_ID, &rev_id);

			if (ret < 0)

				return ret;



			if (0x04 == ((rev_id >> 24) & 0xff))

				ret = regmap_write(maps[desc->ip],

					HW_REVISION_ID, (~val & desc->mask));

			else

				ret = regmap_update_bits(maps[desc->ip],

					desc->reg, desc->mask, val);

		} else

			ret = regmap_update_bits(maps[desc->ip], desc->reg,

				desc->mask, val);

drivers/pinctrl/aspeed/pinctrl-aspeed.h

+1 −0
Original line number Diff line number Diff line
@@ -251,6 +251,7 @@ 
#define SCU3C           0x3C /* System Reset Control/Status Register */

#define SCU48           0x48 /* MAC Interface Clock Delay Setting */

#define HW_STRAP1       0x70 /* AST2400 strapping is 33 bits, is split */

#define HW_REVISION_ID  0x7C /* Silicon revision ID register */

#define SCU80           0x80 /* Multi-function Pin Control #1 */

#define SCU84           0x84 /* Multi-function Pin Control #2 */

#define SCU88           0x88 /* Multi-function Pin Control #3 */