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Commit 1836c3de authored by Skylar Chang's avatar Skylar Chang
Browse files

msm: ipa: disable in order GSI transactions 



IPAv4 has a HW limitation which causes GSI in order transactions
to not complete in order.
Need to ensure SW uses out of order transactions only.

Change-Id: I8cf4f9dfc15e8a405aac23e6491350bee2859fc0
Acked-by: default avatarAdy Abraham <adya@qti.qualcomm.com>
Signed-off-by: default avatarSkylar Chang <chiaweic@codeaurora.org>
parent 1d8d4e8d

drivers/platform/msm/ipa/ipa_v3/ipa_utils.c

+23 −0
Original line number Diff line number Diff line
@@ -2585,6 +2585,29 @@ static void ipa_comp_cfg(void) 
		IPADBG("ipa_qmb_select_by_address_cons_en = %d\n",

				comp_cfg.ipa_qmb_select_by_address_cons_en);

	}



	if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0) {

		ipahal_read_reg_fields(IPA_COMP_CFG, &comp_cfg);

		IPADBG("Before comp config\n");

		IPADBG("gsi_multi_inorder_rd_dis = %d\n",

			comp_cfg.gsi_multi_inorder_rd_dis);



		IPADBG("gsi_multi_inorder_wr_dis = %d\n",

			comp_cfg.gsi_multi_inorder_wr_dis);



		comp_cfg.gsi_multi_inorder_rd_dis = true;

		comp_cfg.gsi_multi_inorder_wr_dis = true;



		ipahal_write_reg_fields(IPA_COMP_CFG, &comp_cfg);



		ipahal_read_reg_fields(IPA_COMP_CFG, &comp_cfg);

		IPADBG("After comp config\n");

		IPADBG("gsi_multi_inorder_rd_dis = %d\n",

			comp_cfg.gsi_multi_inorder_rd_dis);



		IPADBG("gsi_multi_inorder_wr_dis = %d\n",

			comp_cfg.gsi_multi_inorder_wr_dis);

	}

}



/**