Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 180caff8 authored by Akash Asthana's avatar Akash Asthana Committed by Mitul Golani
Browse files

serial: msm_geni_serial: Add support for active pinctrl state 



This change helps configuring GPIO to non UART function which makes
them to stay low when not in use. Kernel framework considers default
state to configure GPIOs during probe.

Adding active pinctrl node for the active configuration set and current
default configuration will be used during the probe time.

Change-Id: Ib26b36876b9c69971dcfe723b269e50026f87e82
Signed-off-by: default avatarAkash Asthana <akashast@codeaurora.org>
parent ddd8ee59

Documentation/devicetree/bindings/serial/qcom,msm-geni-uart.txt

+8 −6
Original line number Diff line number Diff line
@@ -12,9 +12,10 @@ Required properties: 
- reg: Should contain UART register location and length.

- interrupts: Should contain UART core interrupts.

- clocks: clocks needed for UART, includes the core and AHB clock.

- pinctrl-names/pinctrl-0/1: The GPIOs assigned to this core. The names

  Should be "active" and "sleep" for the pin confuguration when core is active

  or when entering sleep state.

- pinctrl-names/pinctrl-0/1/2: The GPIOs assigned to this core. The names

  should be "default", "active" and "sleep" for the pin confuguration.

  It should be in "default" for the default pin configuration during probe,

  in "active" when core is active or in "sleep" when entering in sleep state.

- qcom,wrapper-core: Wrapper QUPv3 core containing this UART controller.



Optional properties:
@@ -29,9 +30,10 @@ qupv3_uart11: qcom,qup_uart@0xa88000 { 
	clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>,

		<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

		<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

	pinctrl-names = "default", "sleep";

	pinctrl-0 = <&qup_1_uart_3_active>;

	pinctrl-1 = <&qup_1_uart_3_sleep>;

	pinctrl-names = "default", "active", "sleep";

	pinctrl-0 = <&qup_1_uart_3_default>;

	pinctrl-1 = <&qup_1_uart_3_active>;

	pinctrl-2 = <&qup_1_uart_3_sleep>;

	interrupts = <0 355 0>;

	qcom,wrapper-core = <&qupv3_0>;

	qcom,wakeup-byte = <0xFF>;

drivers/tty/serial/msm_geni_serial.c

+14 −4
Original line number Diff line number Diff line
@@ -2467,6 +2467,15 @@ static int msm_geni_serial_probe(struct platform_device *pdev) 
		ret = PTR_ERR(dev_port->serial_rsc.geni_pinctrl);

		goto exit_geni_serial_probe;

	}

	dev_port->serial_rsc.geni_gpio_active =

		pinctrl_lookup_state(dev_port->serial_rsc.geni_pinctrl,

							PINCTRL_ACTIVE);



	if (IS_ERR_OR_NULL(dev_port->serial_rsc.geni_gpio_active)) {

		/*

		 * Backward compatible : In case few chips doesn't have ACTIVE

		 * state defined.

		 */

		dev_port->serial_rsc.geni_gpio_active =

			pinctrl_lookup_state(dev_port->serial_rsc.geni_pinctrl,

							PINCTRL_DEFAULT);
@@ -2475,6 +2484,7 @@ static int msm_geni_serial_probe(struct platform_device *pdev) 
			ret = PTR_ERR(dev_port->serial_rsc.geni_gpio_active);

			goto exit_geni_serial_probe;

		}

	}



	/*

	 * For clients who setup an Inband wakeup, leave the GPIO pins

include/linux/qcom-geni-se.h

+1 −0
Original line number Diff line number Diff line
@@ -82,6 +82,7 @@ struct se_geni_rsc { 
};



#define PINCTRL_DEFAULT	"default"

#define PINCTRL_ACTIVE	"active"

#define PINCTRL_SLEEP	"sleep"



#define KHz(freq) (1000 * (freq))