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Commit 17e9273a authored Jun 18, 2015 by Rhyland Klein Committed by Thierry Reding Dec 17, 2015

clk: tegra: pll: Add dyn_ramp callback



Add a callback to the pll_params for custom dynamic ramping
functions which can be specified per PLL.

Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

parent b985114e

drivers/clk/tegra/clk-pll.c

+7 −0

Original line number	Diff line number	Diff line
		@@ -669,6 +669,13 @@ static int _program_pll(struct clk_hw hw, struct tegra_clk_pll_freq_table cfg,

		_get_pll_mnp(pll, &old_cfg);

		if (state && pll->params->defaults_set && pll->params->dyn_ramp &&
		(cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) {
		ret = pll->params->dyn_ramp(pll, cfg);
		if (!ret)
		return 0;
		}

		if (state)
		_clk_pll_disable(hw);

drivers/clk/tegra/clk.h

+4 −0

Original line number	Diff line number	Diff line
		@@ -213,6 +213,8 @@ struct tegra_clk_pll;
		* is already enabled, it will be done the first
		* time the rate is changed while the PLL is
		* disabled.
		* @dyn_ramp: Callback which can be used to define a custom
		* dynamic ramp function for a given PLL.
		*
		* Flags:
		* TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
		@@ -284,6 +286,8 @@ struct tegra_clk_pll_params {
		unsigned long (adjust_vco)(struct tegra_clk_pll_params pll_params,
		unsigned long parent_rate);
		void (set_defaults)(struct tegra_clk_pll pll);
		int (dyn_ramp)(struct tegra_clk_pll pll,
		struct tegra_clk_pll_freq_table *cfg);
		};

		#define TEGRA_PLL_USE_LOCK BIT(0)