clk: qcom: gcc: Update post div value for emac_clk_src



Post div value selected for 5MHz is greater than the
maximum supported div value. Update the same by adding
M and N divider.

Change-Id: I3cdd175bf4b6b6792ab767c7a1e65710608e0682
Signed-off-by: Shefali Jain <shefjain@codeaurora.org>

parent 4dd3d655

drivers/clk/qcom/gcc-qcs405.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -835,7 +835,7 @@ static struct clk_rcg2 byte0_clk_src = {
		};

		static const struct freq_tbl ftbl_emac_clk_src[] = {
		F(5000000, P_GPLL1_OUT_MAIN, 100, 0, 0),
		F(5000000, P_GPLL1_OUT_MAIN, 2, 1, 50),
		F(50000000, P_GPLL1_OUT_MAIN, 10, 0, 0),
		F(125000000, P_GPLL1_OUT_MAIN, 4, 0, 0),
		F(250000000, P_GPLL1_OUT_MAIN, 2, 0, 0),