Loading drivers/clk/qcom/clk-smd-rpm.c +1 −7 Original line number Diff line number Diff line Loading @@ -610,10 +610,8 @@ DEFINE_CLK_SMD_RPM(qcs405, bimc_gpu_clk, bimc_gpu_a_clk, /* SMD_XO_BUFFER */ DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs405, ln_bb_clk, ln_bb_clk_a, 8); DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs405, rf_clk1, rf_clk1_a, 4); DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs405, rf_clk3, rf_clk3_a, 6); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs405, ln_bb_clk_pin, ln_bb_clk_a_pin, 8); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs405, rf_clk1_pin, rf_clk1_a_pin, 4); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs405, rf_clk3_pin, rf_clk3_a_pin, 6); /* Voter clocks */ static DEFINE_CLK_VOTER(pnoc_msmbus_clk, pnoc_clk, LONG_MAX); Loading Loading @@ -664,10 +662,6 @@ static struct clk_hw *qcs405_clks[] = { [RPM_SMD_RF_CLK1_A] = &qcs405_rf_clk1_a.hw, [RPM_SMD_RF_CLK1_PIN] = &qcs405_rf_clk1_pin.hw, [RPM_SMD_RF_CLK1_A_PIN] = &qcs405_rf_clk1_a_pin.hw, [RPM_SMD_RF_CLK3] = &qcs405_rf_clk3.hw, [RPM_SMD_RF_CLK3_A] = &qcs405_rf_clk3_a.hw, [RPM_SMD_RF_CLK3_PIN] = &qcs405_rf_clk3_pin.hw, [RPM_SMD_RF_CLK3_A_PIN] = &qcs405_rf_clk3_a_pin.hw, [RPM_SMD_LN_BB_CLK] = &qcs405_ln_bb_clk.hw, [RPM_SMD_LN_BB_CLK_A] = &qcs405_ln_bb_clk_a.hw, [RPM_SMD_LN_BB_CLK_PIN] = &qcs405_ln_bb_clk_pin.hw, Loading Loading @@ -711,7 +705,7 @@ static struct clk_hw *qcs405_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_qcs405 = { .clks = qcs405_clks, .num_rpm_clks = RPM_SMD_RF_CLK3_A_PIN, .num_rpm_clks = RPM_SMD_LN_BB_CLK_A_PIN, .num_clks = ARRAY_SIZE(qcs405_clks), }; Loading Loading
drivers/clk/qcom/clk-smd-rpm.c +1 −7 Original line number Diff line number Diff line Loading @@ -610,10 +610,8 @@ DEFINE_CLK_SMD_RPM(qcs405, bimc_gpu_clk, bimc_gpu_a_clk, /* SMD_XO_BUFFER */ DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs405, ln_bb_clk, ln_bb_clk_a, 8); DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs405, rf_clk1, rf_clk1_a, 4); DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs405, rf_clk3, rf_clk3_a, 6); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs405, ln_bb_clk_pin, ln_bb_clk_a_pin, 8); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs405, rf_clk1_pin, rf_clk1_a_pin, 4); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs405, rf_clk3_pin, rf_clk3_a_pin, 6); /* Voter clocks */ static DEFINE_CLK_VOTER(pnoc_msmbus_clk, pnoc_clk, LONG_MAX); Loading Loading @@ -664,10 +662,6 @@ static struct clk_hw *qcs405_clks[] = { [RPM_SMD_RF_CLK1_A] = &qcs405_rf_clk1_a.hw, [RPM_SMD_RF_CLK1_PIN] = &qcs405_rf_clk1_pin.hw, [RPM_SMD_RF_CLK1_A_PIN] = &qcs405_rf_clk1_a_pin.hw, [RPM_SMD_RF_CLK3] = &qcs405_rf_clk3.hw, [RPM_SMD_RF_CLK3_A] = &qcs405_rf_clk3_a.hw, [RPM_SMD_RF_CLK3_PIN] = &qcs405_rf_clk3_pin.hw, [RPM_SMD_RF_CLK3_A_PIN] = &qcs405_rf_clk3_a_pin.hw, [RPM_SMD_LN_BB_CLK] = &qcs405_ln_bb_clk.hw, [RPM_SMD_LN_BB_CLK_A] = &qcs405_ln_bb_clk_a.hw, [RPM_SMD_LN_BB_CLK_PIN] = &qcs405_ln_bb_clk_pin.hw, Loading Loading @@ -711,7 +705,7 @@ static struct clk_hw *qcs405_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_qcs405 = { .clks = qcs405_clks, .num_rpm_clks = RPM_SMD_RF_CLK3_A_PIN, .num_rpm_clks = RPM_SMD_LN_BB_CLK_A_PIN, .num_clks = ARRAY_SIZE(qcs405_clks), }; Loading