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Commit 163f22dc authored by Claudiu Manoil's avatar Claudiu Manoil Committed by Kumar Gala
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powerpc/85xx: Fix sram_offset parameter type 



The sram_offset parameter represents a physical address and should be of
type phys_addr_t. As part of this fix, the extraction of sram_params is
being cleaned-up and fixed.

This patch fixes now the case when the offset value of 0xfff00000 was being
rejected by the driver (returning -EINVAL), although this is a valid offset
value.

Signed-off-by: default avatarTang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: default avatarClaudiu Manoil <claudiu.manoil@freescale.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent e1bd5d8b

arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h

+2 −2
Original line number Original line Diff line number Diff line 
/*

/*

 * Copyright 2009-2010 Freescale Semiconductor, Inc

 * Copyright 2009-2010, 2012 Freescale Semiconductor, Inc

 *

 *

 * QorIQ based Cache Controller Memory Mapped Registers

 * QorIQ based Cache Controller Memory Mapped Registers

 *

 *
@@ -91,7 +91,7 @@ struct mpc85xx_l2ctlr { 




struct sram_parameters {

struct sram_parameters {

	unsigned int sram_size;

	unsigned int sram_size;

	uint64_t sram_offset;

	phys_addr_t sram_offset;

};

};





extern int instantiate_cache_sram(struct platform_device *dev,

extern int instantiate_cache_sram(struct platform_device *dev,

arch/powerpc/sysdev/fsl_85xx_l2ctlr.c

+14 −25
Original line number Original line Diff line number Diff line 
/*

/*

 * Copyright 2009-2010 Freescale Semiconductor, Inc.

 * Copyright 2009-2010, 2012 Freescale Semiconductor, Inc.

 *

 *

 * QorIQ (P1/P2) L2 controller init for Cache-SRAM instantiation

 * QorIQ (P1/P2) L2 controller init for Cache-SRAM instantiation

 *

 *
@@ -31,24 +31,21 @@ static char *sram_size; 
static char *sram_offset;

static char *sram_offset;

struct mpc85xx_l2ctlr __iomem *l2ctlr;

struct mpc85xx_l2ctlr __iomem *l2ctlr;





static long get_cache_sram_size(void)

static int get_cache_sram_params(struct sram_parameters *sram_params)

{

{

	unsigned long val;

	unsigned long long addr;

	unsigned int size;





	if (!sram_size || (strict_strtoul(sram_size, 0, &val) < 0))

	if (!sram_size || (kstrtouint(sram_size, 0, &size) < 0))

		return -EINVAL;

		return -EINVAL;





	return val;

	if (!sram_offset || (kstrtoull(sram_offset, 0, &addr) < 0))

}



static long get_cache_sram_offset(void)

{

	unsigned long val;



	if (!sram_offset || (strict_strtoul(sram_offset, 0, &val) < 0))

		return -EINVAL;

		return -EINVAL;





	return val;

	sram_params->sram_offset = addr;

	sram_params->sram_size = size;



	return 0;

}

}





static int __init get_size_from_cmdline(char *str)

static int __init get_size_from_cmdline(char *str)
@@ -93,17 +90,9 @@ static int __devinit mpc85xx_l2ctlr_of_probe(struct platform_device *dev) 
	}

	}

	l2cache_size = *prop;

	l2cache_size = *prop;





	sram_params.sram_size  = get_cache_sram_size();

	if (get_cache_sram_params(&sram_params)) {

	if ((int)sram_params.sram_size <= 0) {

		dev_err(&dev->dev,

			"Entire L2 as cache, Aborting Cache-SRAM stuff\n");

		return -EINVAL;

	}



	sram_params.sram_offset  = get_cache_sram_offset();

	if ((int64_t)sram_params.sram_offset <= 0) {

		dev_err(&dev->dev,

		dev_err(&dev->dev,

			"Entire L2 as cache, provide a valid sram offset\n");

			"Entire L2 as cache, provide valid sram offset and size\n");

		return -EINVAL;

		return -EINVAL;

	}

	}
@@ -125,14 +114,14 @@ static int __devinit mpc85xx_l2ctlr_of_probe(struct platform_device *dev) 
	 * Write bits[0-17] to srbar0

	 * Write bits[0-17] to srbar0

	 */

	 */

	out_be32(&l2ctlr->srbar0,

	out_be32(&l2ctlr->srbar0,

		sram_params.sram_offset & L2SRAM_BAR_MSK_LO18);

		lower_32_bits(sram_params.sram_offset) & L2SRAM_BAR_MSK_LO18);





	/*

	/*

	 * Write bits[18-21] to srbare0

	 * Write bits[18-21] to srbare0

	 */

	 */

#ifdef CONFIG_PHYS_64BIT

#ifdef CONFIG_PHYS_64BIT

	out_be32(&l2ctlr->srbarea0,

	out_be32(&l2ctlr->srbarea0,

		(sram_params.sram_offset >> 32) & L2SRAM_BARE_MSK_HI4);

		upper_32_bits(sram_params.sram_offset) & L2SRAM_BARE_MSK_HI4);

#endif

#endif





	clrsetbits_be32(&l2ctlr->ctl, L2CR_L2E, L2CR_L2FI);

	clrsetbits_be32(&l2ctlr->ctl, L2CR_L2E, L2CR_L2FI);