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Commit 163e589d authored by Arnaldo Carvalho de Melo's avatar Arnaldo Carvalho de Melo
Browse files

perf tools: Move ia64 barrier.h stuff to tools/arch/ia64/include/asm/barrier.h 

We will need it for atomic.h, so move it from the ad-hoc tools/perf/
place to a tools/ subset of the kernel arch/ hierarchy.

Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: David Ahern <dsahern@gmail.com>
Cc: Don Zickus <dzickus@redhat.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Stephane Eranian <eranian@google.com>
Link: http://lkml.kernel.org/n/tip-4op0qdukegrdumyefz4icxk0@git.kernel.org


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 0da85d1e

tools/arch/ia64/include/asm/barrier.h

0 → 100644
+48 −0
Original line number Diff line number Diff line 
/*

 * Copied from the kernel sources to tools/:

 *

 * Memory barrier definitions.  This is based on information published

 * in the Processor Abstraction Layer and the System Abstraction Layer

 * manual.

 *

 * Copyright (C) 1998-2003 Hewlett-Packard Co

 *	David Mosberger-Tang <davidm@hpl.hp.com>

 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>

 * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>

 */

#ifndef _TOOLS_LINUX_ASM_IA64_BARRIER_H

#define _TOOLS_LINUX_ASM_IA64_BARRIER_H



#include <linux/compiler.h>



/*

 * Macros to force memory ordering.  In these descriptions, "previous"

 * and "subsequent" refer to program order; "visible" means that all

 * architecturally visible effects of a memory access have occurred

 * (at a minimum, this means the memory has been read or written).

 *

 *   wmb():	Guarantees that all preceding stores to memory-

 *		like regions are visible before any subsequent

 *		stores and that all following stores will be

 *		visible only after all previous stores.

 *   rmb():	Like wmb(), but for reads.

 *   mb():	wmb()/rmb() combo, i.e., all previous memory

 *		accesses are visible before all subsequent

 *		accesses and vice versa.  This is also known as

 *		a "fence."

 *

 * Note: "mb()" and its variants cannot be used as a fence to order

 * accesses to memory mapped I/O registers.  For that, mf.a needs to

 * be used.  However, we don't want to always use mf.a because (a)

 * it's (presumably) much slower than mf and (b) mf.a is supported for

 * sequential memory pages only.

 */



/* XXX From arch/ia64/include/uapi/asm/gcc_intrin.h */

#define ia64_mf()       asm volatile ("mf" ::: "memory")



#define mb()		ia64_mf()

#define rmb()		mb()

#define wmb()		mb()



#endif /* _TOOLS_LINUX_ASM_IA64_BARRIER_H */

tools/include/asm/barrier.h

+2 −0
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@@ -10,4 +10,6 @@ 
#include "../../arch/sparc/include/asm/barrier.h"

#elif defined(__alpha__)

#include "../../arch/alpha/include/asm/barrier.h"

#elif defined(__ia64__)

#include "../../arch/ia64/include/asm/barrier.h"

#endif

tools/perf/MANIFEST

+1 −0
Original line number Diff line number Diff line 
tools/perf

tools/arch/alpha/include/asm/barrier.h

tools/arch/ia64/include/asm/barrier.h

tools/arch/powerpc/include/asm/barrier.h

tools/arch/s390/include/asm/barrier.h

tools/arch/sh/include/asm/barrier.h

tools/perf/perf-sys.h

+0 −3
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@@ -65,9 +65,6 @@ 
#endif



#ifdef __ia64__

#define mb()		asm volatile ("mf" ::: "memory")

#define wmb()		asm volatile ("mf" ::: "memory")

#define rmb()		asm volatile ("mf" ::: "memory")

#define cpu_relax()	asm volatile ("hint @pause" ::: "memory")

#define CPUINFO_PROC	{"model name"}

#endif