Loading drivers/clk/qcom/gcc-sm8150.c +2 −0 Original line number Diff line number Diff line Loading @@ -4161,6 +4161,8 @@ static const struct qcom_reset_map gcc_sm8150_resets[] = { [GCC_USB30_SEC_BCR] = { 0x10000 }, [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, [GCC_VIDEO_AXIC_CLK_BCR] = { 0xb02c, 2 }, [GCC_VIDEO_AXI0_CLK_BCR] = { 0xb024, 2 }, [GCC_VIDEO_AXI1_CLK_BCR] = { 0xb028, 2 }, }; Loading include/dt-bindings/clock/qcom,gcc-sm8150.h +3 −1 Original line number Diff line number Diff line /* * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading Loading @@ -248,6 +248,8 @@ #define GCC_USB30_SEC_BCR 27 #define GCC_USB_PHY_CFG_AHB2PHY_BCR 28 #define GCC_VIDEO_AXIC_CLK_BCR 29 #define GCC_VIDEO_AXI0_CLK_BCR 30 #define GCC_VIDEO_AXI1_CLK_BCR 31 /* Dummy clocks for rate measurement */ #define MEASURE_ONLY_SNOC_CLK 0 Loading Loading
drivers/clk/qcom/gcc-sm8150.c +2 −0 Original line number Diff line number Diff line Loading @@ -4161,6 +4161,8 @@ static const struct qcom_reset_map gcc_sm8150_resets[] = { [GCC_USB30_SEC_BCR] = { 0x10000 }, [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, [GCC_VIDEO_AXIC_CLK_BCR] = { 0xb02c, 2 }, [GCC_VIDEO_AXI0_CLK_BCR] = { 0xb024, 2 }, [GCC_VIDEO_AXI1_CLK_BCR] = { 0xb028, 2 }, }; Loading
include/dt-bindings/clock/qcom,gcc-sm8150.h +3 −1 Original line number Diff line number Diff line /* * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading Loading @@ -248,6 +248,8 @@ #define GCC_USB30_SEC_BCR 27 #define GCC_USB_PHY_CFG_AHB2PHY_BCR 28 #define GCC_VIDEO_AXIC_CLK_BCR 29 #define GCC_VIDEO_AXI0_CLK_BCR 30 #define GCC_VIDEO_AXI1_CLK_BCR 31 /* Dummy clocks for rate measurement */ #define MEASURE_ONLY_SNOC_CLK 0 Loading