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Commit 160614a2 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
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drm/i915: Disable RC6 before configuring in on VLV/CHV 



Follow the sequence in the BIOS spec and clear the RC_CONTROL register
before changing any of the other RC6/RP registers.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarDeepak <S&lt;deepak.s@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 095acd5f

drivers/gpu/drm/i915/intel_pm.c

+6 −0
Original line number Diff line number Diff line
@@ -4712,6 +4712,9 @@ static void cherryview_enable_rps(struct drm_device *dev) 
	 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/

	gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);



	/*  Disable RC states. */

	I915_WRITE(GEN6_RC_CONTROL, 0);



	/* 2a: Program RC6 thresholds.*/

	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);

	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
@@ -4801,6 +4804,9 @@ static void valleyview_enable_rps(struct drm_device *dev) 
	/* If VLV, Forcewake all wells, else re-direct to regular path */

	gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);



	/*  Disable RC states. */

	I915_WRITE(GEN6_RC_CONTROL, 0);



	I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);

	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);

	I915_WRITE(GEN6_RP_UP_EI, 66000);