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Commit 1589037f authored by Hans Verkuil's avatar Hans Verkuil Committed by Mauro Carvalho Chehab
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[media] saa7115: add support for double-rate ASCLK 



Some devices expect a double rate ASCLK. Add a flag to let the driver know
through the s_crystal_freq call.

Signed-off-by: default avatarHans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@redhat.com>
parent c875dee5

drivers/media/i2c/saa7115.c

+11 −5
Original line number Diff line number Diff line
@@ -83,9 +83,10 @@ struct saa711x_state { 
	u32 ident;

	u32 audclk_freq;

	u32 crystal_freq;

	u8 ucgc;

	bool ucgc;

	u8 cgcdiv;

	u8 apll;

	bool apll;

	bool double_asclk;

};



static inline struct saa711x_state *to_state(struct v4l2_subdev *sd)
@@ -732,8 +733,12 @@ static int saa711x_s_clock_freq(struct v4l2_subdev *sd, u32 freq) 
	if (state->apll)

		acc |= 0x08;



	if (state->double_asclk) {

		acpf <<= 1;

		acni <<= 1;

	}

	saa711x_write(sd, R_38_CLK_RATIO_AMXCLK_TO_ASCLK, 0x03);

	saa711x_write(sd, R_39_CLK_RATIO_ASCLK_TO_ALRCLK, 0x10);

	saa711x_write(sd, R_39_CLK_RATIO_ASCLK_TO_ALRCLK, 0x10 << state->double_asclk);

	saa711x_write(sd, R_3A_AUD_CLK_GEN_BASIC_SETUP, acc);



	saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD, acpf & 0xff);
@@ -1302,9 +1307,10 @@ static int saa711x_s_crystal_freq(struct v4l2_subdev *sd, u32 freq, u32 flags) 
	if (freq != SAA7115_FREQ_32_11_MHZ && freq != SAA7115_FREQ_24_576_MHZ)

		return -EINVAL;

	state->crystal_freq = freq;

	state->double_asclk = flags & SAA7115_FREQ_FL_DOUBLE_ASCLK;

	state->cgcdiv = (flags & SAA7115_FREQ_FL_CGCDIV) ? 3 : 4;

	state->ucgc = (flags & SAA7115_FREQ_FL_UCGC) ? 1 : 0;

	state->apll = (flags & SAA7115_FREQ_FL_APLL) ? 1 : 0;

	state->ucgc = flags & SAA7115_FREQ_FL_UCGC;

	state->apll = flags & SAA7115_FREQ_FL_APLL;

	saa711x_s_clock_freq(sd, state->audclk_freq);

	return 0;

}

include/media/saa7115.h

+4 −3
Original line number Diff line number Diff line
@@ -62,6 +62,7 @@ 
#define SAA7115_FREQ_FL_UCGC         (1 << 0) /* SA 3A[7], UCGC, SAA7115 only */

#define SAA7115_FREQ_FL_CGCDIV       (1 << 1) /* SA 3A[6], CGCDIV, SAA7115 only */

#define SAA7115_FREQ_FL_APLL         (1 << 2) /* SA 3A[3], APLL, SAA7114/5 only */

#define SAA7115_FREQ_FL_DOUBLE_ASCLK (1 << 3) /* SA 39, LRDIV, SAA7114/5 only */



#endif