Loading drivers/clk/qcom/gcc-qcs405.c +0 −28 Original line number Diff line number Diff line Loading @@ -1488,32 +1488,6 @@ static struct clk_branch gcc_blsp1_ahb_clk = { }, }; static struct clk_branch gcc_dcc_clk = { .halt_reg = 0x77004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x77004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_dcc_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_dcc_xo_clk = { .halt_reg = 0x77008, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x77008, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_dcc_xo_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp1_qup0_i2c_apps_clk = { .halt_reg = 0x6028, .halt_check = BRANCH_HALT, Loading Loading @@ -2873,8 +2847,6 @@ static struct clk_regmap *gcc_qcs405_clocks[] = { [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr, [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr, [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, [GCC_DCC_CLK] = &gcc_dcc_clk.clkr, [GCC_DCC_XO_CLK] = &gcc_dcc_xo_clk.clkr, }; static const struct qcom_reset_map gcc_qcs405_resets[] = { Loading include/dt-bindings/clock/qcom,gcc-qcs405.h +0 −2 Original line number Diff line number Diff line Loading @@ -70,7 +70,6 @@ #define GCC_BLSP2_QUP0_SPI_APPS_CLK 53 #define GCC_BLSP2_UART0_APPS_CLK 54 #define GCC_BOOT_ROM_AHB_CLK 55 #define GCC_DCC_CLK 56 #define GCC_GENI_IR_H_CLK 57 #define GCC_ETH_AXI_CLK 58 #define GCC_ETH_PTP_CLK 59 Loading Loading @@ -154,7 +153,6 @@ #define GCC_CRYPTO_CLK 137 #define GCC_MDP_TBU_CLK 138 #define GCC_QDSS_DAP_CLK 139 #define GCC_DCC_XO_CLK 140 #define GCC_GENI_IR_BCR 0 #define GCC_USB_HS_BCR 1 Loading Loading
drivers/clk/qcom/gcc-qcs405.c +0 −28 Original line number Diff line number Diff line Loading @@ -1488,32 +1488,6 @@ static struct clk_branch gcc_blsp1_ahb_clk = { }, }; static struct clk_branch gcc_dcc_clk = { .halt_reg = 0x77004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x77004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_dcc_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_dcc_xo_clk = { .halt_reg = 0x77008, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x77008, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_dcc_xo_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch gcc_blsp1_qup0_i2c_apps_clk = { .halt_reg = 0x6028, .halt_check = BRANCH_HALT, Loading Loading @@ -2873,8 +2847,6 @@ static struct clk_regmap *gcc_qcs405_clocks[] = { [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr, [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr, [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, [GCC_DCC_CLK] = &gcc_dcc_clk.clkr, [GCC_DCC_XO_CLK] = &gcc_dcc_xo_clk.clkr, }; static const struct qcom_reset_map gcc_qcs405_resets[] = { Loading
include/dt-bindings/clock/qcom,gcc-qcs405.h +0 −2 Original line number Diff line number Diff line Loading @@ -70,7 +70,6 @@ #define GCC_BLSP2_QUP0_SPI_APPS_CLK 53 #define GCC_BLSP2_UART0_APPS_CLK 54 #define GCC_BOOT_ROM_AHB_CLK 55 #define GCC_DCC_CLK 56 #define GCC_GENI_IR_H_CLK 57 #define GCC_ETH_AXI_CLK 58 #define GCC_ETH_PTP_CLK 59 Loading Loading @@ -154,7 +153,6 @@ #define GCC_CRYPTO_CLK 137 #define GCC_MDP_TBU_CLK 138 #define GCC_QDSS_DAP_CLK 139 #define GCC_DCC_XO_CLK 140 #define GCC_GENI_IR_BCR 0 #define GCC_USB_HS_BCR 1 Loading