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Commit 1543b765 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'mlx4-fixes' 



Or Gerlitz says:

====================
Mellanox 10/40G mlx4 driver fixes for 4.5-rc

Bunch of fixes from the team to the mlx4 Eth and core drivers.

Series generated against net commit aac8d3c2 "qmi_wwan: add "4G LTE usb-modem U901""

Please push patches 1,2 and 6 to -stable  as well

changes from v0:
 - handled another wrongly accounted HW counter in patch #1 (Rick)
 - fixed coding style issues in patch #4 (Sergei)
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents aac8d3c2 925ab1aa

drivers/infiniband/hw/mlx4/qp.c

+5 −2
Original line number Diff line number Diff line
@@ -1681,9 +1681,12 @@ static int __mlx4_ib_modify_qp(struct ib_qp *ibqp, 
	}



	if (qp->ibqp.uobject)

		context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);

		context->usr_page = cpu_to_be32(

			mlx4_to_hw_uar_index(dev->dev,

					     to_mucontext(ibqp->uobject->context)->uar.index));

	else

		context->usr_page = cpu_to_be32(dev->priv_uar.index);

		context->usr_page = cpu_to_be32(

			mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index));



	if (attr_mask & IB_QP_DEST_QPN)

		context->remote_qpn = cpu_to_be32(attr->dest_qp_num);

drivers/net/ethernet/mellanox/mlx4/catas.c

+9 −2
Original line number Diff line number Diff line
@@ -182,10 +182,17 @@ void mlx4_enter_error_state(struct mlx4_dev_persistent *persist) 
		err = mlx4_reset_slave(dev);

	else

		err = mlx4_reset_master(dev);

	BUG_ON(err != 0);



	dev->persist->state |= MLX4_DEVICE_STATE_INTERNAL_ERROR;

	if (!err) {

		mlx4_err(dev, "device was reset successfully\n");

	} else {

		/* EEH could have disabled the PCI channel during reset. That's

		 * recoverable and the PCI error flow will handle it.

		 */

		if (!pci_channel_offline(dev->persist->pdev))

			BUG_ON(1);

	}

	dev->persist->state |= MLX4_DEVICE_STATE_INTERNAL_ERROR;

	mutex_unlock(&persist->device_state_mutex);



	/* At that step HW was already reset, now notify clients */

drivers/net/ethernet/mellanox/mlx4/cq.c

+3 −1
Original line number Diff line number Diff line
@@ -318,7 +318,9 @@ int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, 
	if (timestamp_en)

		cq_context->flags  |= cpu_to_be32(1 << 19);



	cq_context->logsize_usrpage = cpu_to_be32((ilog2(nent) << 24) | uar->index);

	cq_context->logsize_usrpage =

		cpu_to_be32((ilog2(nent) << 24) |

			    mlx4_to_hw_uar_index(dev, uar->index));

	cq_context->comp_eqn	    = priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(vector)].eqn;

	cq_context->log_page_size   = mtt->page_shift - MLX4_ICM_PAGE_SHIFT;

drivers/net/ethernet/mellanox/mlx4/en_clock.c

+19 −6
Original line number Diff line number Diff line
@@ -236,6 +236,24 @@ static const struct ptp_clock_info mlx4_en_ptp_clock_info = { 
	.enable		= mlx4_en_phc_enable,

};



#define MLX4_EN_WRAP_AROUND_SEC	10ULL



/* This function calculates the max shift that enables the user range

 * of MLX4_EN_WRAP_AROUND_SEC values in the cycles register.

 */

static u32 freq_to_shift(u16 freq)

{

	u32 freq_khz = freq * 1000;

	u64 max_val_cycles = freq_khz * 1000 * MLX4_EN_WRAP_AROUND_SEC;

	u64 max_val_cycles_rounded = is_power_of_2(max_val_cycles + 1) ?

		max_val_cycles : roundup_pow_of_two(max_val_cycles) - 1;

	/* calculate max possible multiplier in order to fit in 64bit */

	u64 max_mul = div_u64(0xffffffffffffffffULL, max_val_cycles_rounded);



	/* This comes from the reverse of clocksource_khz2mult */

	return ilog2(div_u64(max_mul * freq_khz, 1000000));

}



void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev)

{

	struct mlx4_dev *dev = mdev->dev;
@@ -254,12 +272,7 @@ void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev) 
	memset(&mdev->cycles, 0, sizeof(mdev->cycles));

	mdev->cycles.read = mlx4_en_read_clock;

	mdev->cycles.mask = CLOCKSOURCE_MASK(48);

	/* Using shift to make calculation more accurate. Since current HW

	 * clock frequency is 427 MHz, and cycles are given using a 48 bits

	 * register, the biggest shift when calculating using u64, is 14

	 * (max_cycles * multiplier < 2^64)

	 */

	mdev->cycles.shift = 14;

	mdev->cycles.shift = freq_to_shift(dev->caps.hca_core_clock);

	mdev->cycles.mult =

		clocksource_khz2mult(1000 * dev->caps.hca_core_clock, mdev->cycles.shift);

	mdev->nominal_c_mult = mdev->cycles.mult;

drivers/net/ethernet/mellanox/mlx4/en_netdev.c

+5 −4
Original line number Diff line number Diff line
@@ -2344,8 +2344,6 @@ static void mlx4_en_add_vxlan_offloads(struct work_struct *work) 
	/* set offloads */

	priv->dev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM |

				      NETIF_F_TSO | NETIF_F_GSO_UDP_TUNNEL;

	priv->dev->hw_features |= NETIF_F_GSO_UDP_TUNNEL;

	priv->dev->features    |= NETIF_F_GSO_UDP_TUNNEL;

}



static void mlx4_en_del_vxlan_offloads(struct work_struct *work)
@@ -2356,8 +2354,6 @@ static void mlx4_en_del_vxlan_offloads(struct work_struct *work) 
	/* unset offloads */

	priv->dev->hw_enc_features &= ~(NETIF_F_IP_CSUM | NETIF_F_RXCSUM |

				      NETIF_F_TSO | NETIF_F_GSO_UDP_TUNNEL);

	priv->dev->hw_features &= ~NETIF_F_GSO_UDP_TUNNEL;

	priv->dev->features    &= ~NETIF_F_GSO_UDP_TUNNEL;



	ret = mlx4_SET_PORT_VXLAN(priv->mdev->dev, priv->port,

				  VXLAN_STEER_BY_OUTER_MAC, 0);
@@ -2980,6 +2976,11 @@ int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, 
		priv->rss_hash_fn = ETH_RSS_HASH_TOP;

	}



	if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {

		dev->hw_features |= NETIF_F_GSO_UDP_TUNNEL;

		dev->features    |= NETIF_F_GSO_UDP_TUNNEL;

	}



	mdev->pndev[port] = dev;

	mdev->upper[port] = NULL;