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Commit 1525dac3 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge changes I73b7a41b,I29466d14,I6729f1a8,Ia0daac94,Idd532cb7,Id0c136be,Ia4bf290e into msm-next 

* changes:
  tty: serial: msm_geni_serial: Configure the IO control registers
  serial: msm_geni_serial: Modify the Rx state machine initializations
  defconfig: arm64: Enable UART functionality for SDM855
  defconfig: arm64: Enable QUPv3 GENI SE driver for SDM855
  ARM: dts: msm: Add UART related entries for SDM855
  ARM: dts: msm: Add QUPv3 related entries for SDM855
  tty: serial: Add UART driver snapshot for QUPv3 based core
parents f76e59ad 3ffb7e88

Documentation/devicetree/bindings/serial/qcom,msm-geni-uart.txt

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* MSM Serial UART for GENI based cores.



The MSM serial UART driver supports low speed and high speed use-cases.

This is meant only for QUPv3 GENI based cores and isn't backwards compatible.

There is support for console usecases and for higher speed usecases that need

DMA.



Required properties:

- compatible: should contain "qcom,msm-geni-uart, qcom,msm-geni-console"

  for UART console usecases, "qcom,msm-geni-uart, qcom,msm-geni-serial-hs"

  for High Speed (HS) usecases.

- reg: Should contain UART register location and length.

- interrupts: Should contain UART core interrupts.

- clocks: clocks needed for UART, includes the core and AHB clock.

- pinctrl-names/pinctrl-0/1: The GPIOs assigned to this core. The names

  Should be "active" and "sleep" for the pin confuguration when core is active

  or when entering sleep state.

- qcom,wrapper-core: Wrapper QUPv3 core containing this UART controller.



Optional properties:

- qcom,wakeup-byte: Byte to be injected in the tty layer during wakeup isr.



Example:

qupv3_uart11: qcom,qup_uart@0xa88000 {

	compatible = "qcom,msm-geni-uart";

	reg = <0xa88000 0x7000>;

	reg-names = "se_phys";

	clock-names = "se-clk", "m-ahb", "s-ahb";

	clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>,

		<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

		<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

	pinctrl-names = "default", "sleep";

	pinctrl-0 = <&qup_1_uart_3_active>;

	pinctrl-1 = <&qup_1_uart_3_sleep>;

	interrupts = <0 355 0>;

	qcom,wrapper-core = <&qupv3_0>;

	qcom,wakeup-byte = <0xFF>;

};

arch/arm64/boot/dts/qcom/sdm855-cdp.dtsi

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@@ -9,3 +9,7 @@ 
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



&qupv3_se12_2uart {

	status = "ok";

};

arch/arm64/boot/dts/qcom/sdm855-mtp.dtsi

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@@ -9,3 +9,7 @@ 
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



&qupv3_se12_2uart {

	status = "ok";

};

arch/arm64/boot/dts/qcom/sdm855-pinctrl.dtsi

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@@ -65,5 +65,65 @@ 
				output-high; /* active low reset */

			};

		};



		qupv3_se12_2uart_pins: qupv3_se12_2uart_pins {

			qupv3_se12_2uart_active: qupv3_se12_2uart_active {

				mux {

					pins = "gpio85", "gpio86";

					function = "qup10";

				};



				config {

					pins = "gpio85", "gpio86";

					drive-strength = <2>;

					bias-disable;

				};

			};



			qupv3_se12_2uart_sleep: qupv3_se12_2uart_sleep {

				mux {

					pins = "gpio85", "gpio86";

					function = "gpio";

				};



				config {

					pins = "gpio85", "gpio86";

					drive-strength = <2>;

					bias-disable;

				};

			};

		};



		qupv3_se17_4uart_pins: qupv3_se17_4uart_pins {

			qupv3_se17_4uart_active: qupv3_se17_4uart_active {

				mux {

					pins = "gpio43", "gpio44", "gpio45",

								"gpio46";

					function = "qup13";

				};



				config {

					pins = "gpio43", "gpio44", "gpio45",

								"gpio46";

					drive-strength = <2>;

					bias-disable;

				};

			};



			qupv3_se17_4uart_sleep: qupv3_se17_4uart_sleep {

				mux {

					pins = "gpio43", "gpio44", "gpio45",

								"gpio46";

					function = "gpio";

				};



				config {

					pins = "gpio43", "gpio44", "gpio45",

								"gpio46";

					drive-strength = <2>;

					bias-disable;

				};

			};

		};

	};

};

arch/arm64/boot/dts/qcom/sdm855-qupv3.dtsi

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/* Copyright (c) 2017, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#include <dt-bindings/msm/msm-bus-ids.h>



&soc {

	/* QUPv3 South Instances */

	qupv3_0: qcom,qupv3_0_geni_se@8c0000 {

		compatible = "qcom,qupv3-geni-se";

		reg = <0x8c0000 0x6000>;

		qcom,bus-mas-id = <MSM_BUS_MASTER_BLSP_1>;

		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;

		qcom,iommu-s1-bypass;



		iommu_qupv3_0_geni_se_cb: qcom,iommu_qupv3_0_geni_se_cb {

			compatible = "qcom,qupv3-geni-se-cb";

			iommus = <&apps_smmu 0xc3 0x0>;

		};

	};



	/* QUPv3 North Instances */

	qupv3_1: qcom,qupv3_1_geni_se@ac0000 {

		compatible = "qcom,qupv3-geni-se";

		reg = <0xac0000 0x6000>;

		qcom,bus-mas-id = <MSM_BUS_MASTER_BLSP_2>;

		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;

		qcom,iommu-s1-bypass;



		iommu_qupv3_1_geni_se_cb: qcom,iommu_qupv3_1_geni_se_cb {

			compatible = "qcom,qupv3-geni-se-cb";

			iommus = <&apps_smmu 0x603 0x0>;

		};

	};



	/* 2-wire UART */



	/* Debug UART Instance for CDP/MTP platform */

	qupv3_se12_2uart: qcom,qup_uart@0xa90000 {

		compatible = "qcom,msm-geni-console", "qcom,msm-geni-uart";

		reg = <0xa90000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se12_2uart_active>;

		pinctrl-1 = <&qupv3_se12_2uart_sleep>;

		interrupts = <GIC_SPI 357 0>;

		qcom,wrapper-core = <&qupv3_1>;

		status = "disabled";

	};



	/* QUPv3 East Instances */

	qupv3_2: qcom,qupv3_2_geni_se@cc0000 {

		compatible = "qcom,qupv3-geni-se";

		reg = <0xcc0000 0x6000>;

		qcom,bus-mas-id = <MSM_BUS_MASTER_BLSP_2>;

		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;

		qcom,iommu-s1-bypass;



		iommu_qupv3_2_geni_se_cb: qcom,iommu_qupv3_2_geni_se_cb {

			compatible = "qcom,qupv3-geni-se-cb";

			iommus = <&apps_smmu 0x7a3 0x0>;

		};

	};



	/* 4-wire UART */

	qupv3_se17_4uart: qcom,qup_uart@0xc8c000 {

		compatible = "qcom,msm-geni-serial-hs", "qcom,msm-geni-uart";

		reg = <0xc8c000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S3_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se17_4uart_active>;

		pinctrl-1 = <&qupv3_se17_4uart_sleep>;

		interrupts-extended = <GIC_SPI 585 0>,

				<&tlmm 46 0>;

		qcom,wrapper-core = <&qupv3_2>;

		qcom,wakeup-byte = <0xFD>;

		status = "disabled";

	};

};