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Commit 14698b6c authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/gfx: add proper CG flags for fiji 



We were already enabling these CG features, this uses
the standard interface for doing so.

Acked-by: default avatarTom St Denis <tom.stdenis@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4fae91c5

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+48 −34
Original line number Diff line number Diff line
@@ -4317,18 +4317,24 @@ static void fiji_update_medium_grain_clock_gating(struct amdgpu_device *adev, 
	uint32_t temp, data;



	/* It is disabled by HW by default */

	if (enable) {

	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {

		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {

			if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {

				/* 1 - RLC memory Light sleep */

				temp = data = RREG32(mmRLC_MEM_SLP_CNTL);

				data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;

				if (temp != data)

					WREG32(mmRLC_MEM_SLP_CNTL, data);

			}



			if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {

				/* 2 - CP memory Light sleep */

				temp = data = RREG32(mmCP_MEM_SLP_CNTL);

				data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;

				if (temp != data)

					WREG32(mmCP_MEM_SLP_CNTL, data);

			}

		}



		/* 3 - RLC_CGTT_MGCG_OVERRIDE */

		temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
@@ -4346,17 +4352,21 @@ static void fiji_update_medium_grain_clock_gating(struct amdgpu_device *adev, 
		/* 5 - clear mgcg override */

		fiji_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, CLE_BPM_SERDES_CMD);



		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {

			/* 6 - Enable CGTS(Tree Shade) MGCG /MGLS */

			temp = data = RREG32(mmCGTS_SM_CTRL_REG);

			data &= ~(CGTS_SM_CTRL_REG__SM_MODE_MASK);

			data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);

			data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;

			data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;

			if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&

			    (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))

				data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;

			data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;

			data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);

			if (temp != data)

				WREG32(mmCGTS_SM_CTRL_REG, data);

		}

		udelay(50);



		/* 7 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
@@ -4412,7 +4422,7 @@ static void fiji_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 


	temp = data = RREG32(mmRLC_CGCG_CGLS_CTRL);



	if (enable) {

	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {

		/* 1 enable cntx_empty_int_enable/cntx_busy_int_enable/

		 * Cmp_busy/GFX_Idle interrupts

		 */
@@ -4438,6 +4448,7 @@ static void fiji_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 
		/* 5 - enable cgcg */

		data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;



		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {

			/* enable cgls*/

			data |= RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
@@ -4446,6 +4457,9 @@ static void fiji_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 


			if (temp1 != data1)

				WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);

		} else {

			data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;

		}



		if (temp != data)

			WREG32(mmRLC_CGCG_CGLS_CTRL, data);

drivers/gpu/drm/amd/amdgpu/vi.c

+8 −1
Original line number Diff line number Diff line
@@ -1076,7 +1076,14 @@ static int vi_common_early_init(void *handle) 
		adev->external_rev_id = 0x1;

		break;

	case CHIP_FIJI:

		adev->cg_flags = 0;

		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |

			AMD_CG_SUPPORT_GFX_MGLS |

			AMD_CG_SUPPORT_GFX_RLC_LS |

			AMD_CG_SUPPORT_GFX_CP_LS |

			AMD_CG_SUPPORT_GFX_CGTS |

			AMD_CG_SUPPORT_GFX_CGTS_LS |

			AMD_CG_SUPPORT_GFX_CGCG |

			AMD_CG_SUPPORT_GFX_CGLS;

		adev->pg_flags = 0;

		adev->external_rev_id = adev->rev_id + 0x3c;

		break;