Loading arch/arm64/boot/dts/qcom/atoll.dtsi +18 −0 Original line number Diff line number Diff line Loading @@ -1323,6 +1323,24 @@ #mbox-cells = <1>; }; spmi_bus: qcom,spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc440000 0x1100>, <0xc600000 0x2000000>, <0xe600000 0x100000>, <0xe700000 0xa0000>, <0xc40a000 0x26000>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts = <GIC_SPI 481 IRQ_TYPE_NONE>; qcom,ee = <0>; qcom,channel = <0>; #address-cells = <1>; #size-cells = <1>; interrupt-controller; #interrupt-cells = <4>; cell-index = <0>; }; }; #include "atoll-gdsc.dtsi" Loading Loading
arch/arm64/boot/dts/qcom/atoll.dtsi +18 −0 Original line number Diff line number Diff line Loading @@ -1323,6 +1323,24 @@ #mbox-cells = <1>; }; spmi_bus: qcom,spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc440000 0x1100>, <0xc600000 0x2000000>, <0xe600000 0x100000>, <0xe700000 0xa0000>, <0xc40a000 0x26000>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts = <GIC_SPI 481 IRQ_TYPE_NONE>; qcom,ee = <0>; qcom,channel = <0>; #address-cells = <1>; #size-cells = <1>; interrupt-controller; #interrupt-cells = <4>; cell-index = <0>; }; }; #include "atoll-gdsc.dtsi" Loading