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Commit 140fc727 authored by Yinghai Lu's avatar Yinghai Lu Committed by Ingo Molnar
Browse files

x86: cpu/common*.c, merge display_cacheinfo() 



Signed-off-by: default avatarYinghai Lu <yhlu.kernel@gmail.com>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent b9e67f00

arch/x86/kernel/cpu/common.c

+8 −0
Original line number Original line Diff line number Diff line
@@ -285,6 +285,10 @@ void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) 
		printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",

		printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",

				edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);

				edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);

		c->x86_cache_size = (ecx>>24) + (edx>>24);

		c->x86_cache_size = (ecx>>24) + (edx>>24);

#ifdef CONFIG_X86_64

		/* On K8 L1 TLB is inclusive, so don't count it */

		c->x86_tlbsize = 0;

#endif

	}

	}





	if (n < 0x80000006)	/* Some chips just has a large L1. */

	if (n < 0x80000006)	/* Some chips just has a large L1. */
@@ -293,6 +297,9 @@ void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) 
	cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);

	cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);

	l2size = ecx >> 16;

	l2size = ecx >> 16;





#ifdef CONFIG_X86_64

	c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);

#else

	/* do processor-specific cache resizing */

	/* do processor-specific cache resizing */

	if (this_cpu->c_size_cache)

	if (this_cpu->c_size_cache)

		l2size = this_cpu->c_size_cache(c, l2size);

		l2size = this_cpu->c_size_cache(c, l2size);
@@ -303,6 +310,7 @@ void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) 




	if (l2size == 0)

	if (l2size == 0)

		return;		/* Again, no L2 cache is possible */

		return;		/* Again, no L2 cache is possible */

#endif





	c->x86_cache_size = l2size;

	c->x86_cache_size = l2size;

arch/x86/kernel/cpu/common_64.c

+17 −0
Original line number Original line Diff line number Diff line
@@ -285,8 +285,10 @@ void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) 
		printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",

		printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",

				edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);

				edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);

		c->x86_cache_size = (ecx>>24) + (edx>>24);

		c->x86_cache_size = (ecx>>24) + (edx>>24);

#ifdef CONFIG_X86_64

		/* On K8 L1 TLB is inclusive, so don't count it */

		/* On K8 L1 TLB is inclusive, so don't count it */

		c->x86_tlbsize = 0;

		c->x86_tlbsize = 0;

#endif

	}

	}





	if (n < 0x80000006)	/* Some chips just has a large L1. */

	if (n < 0x80000006)	/* Some chips just has a large L1. */
@@ -294,7 +296,22 @@ void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) 




	cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);

	cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);

	l2size = ecx >> 16;

	l2size = ecx >> 16;



#ifdef CONFIG_X86_64

	c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);

	c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);

#else



	/* do processor-specific cache resizing */

	if (this_cpu->c_size_cache)

		l2size = this_cpu->c_size_cache(c, l2size);



	/* Allow user to override all this if necessary. */

	if (cachesize_override != -1)

		l2size = cachesize_override;



	if (l2size == 0)

		return;		/* Again, no L2 cache is possible */

#endif





	c->x86_cache_size = l2size;

	c->x86_cache_size = l2size;