Loading drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.c +6 −1 Original line number Diff line number Diff line Loading @@ -818,9 +818,13 @@ void ipa_save_registers(void) for (i = 0; i < ARRAY_SIZE(ipa_reg_save_gsi_ch_test_bus_selector_array); i++) { ipa_reg_save.gsi.debug.gsi_test_bus.test_bus_selector[i] = ipa_reg_save_gsi_ch_test_bus_selector_array[i]; /* Write test bus selector */ HWIO_GSI_TEST_BUS_SEL_OUT (ipa_reg_save_gsi_ch_test_bus_selector_array[i]); ipa_reg_save.gsi.debug.gsi_test_bus.test_bus_reg[ i].gsi_testbus_reg = (u32)HWIO_GSI_TEST_BUS_REG_IN; Loading Loading @@ -1217,6 +1221,7 @@ static void ipa_hal_save_regs_save_ipa_testbus(void) for (sel_internal = 0; sel_internal <= IPA_TESTBUS_SEL_INTERNAL_PIPE_MAX; sel_internal++) { debug_data_sel.value = 0; debug_data_sel.def.pipe_select = sel_ep; debug_data_sel.def.external_block_select = sel_external; Loading Loading @@ -1269,7 +1274,7 @@ int ipa_reg_save_init(u32 value) ipa3_ctx->ipa_wrapper_base); ipa3_ctx->reg_collection_base = ioremap(ipa3_ctx->ipa_wrapper_base, ioremap_nocache(ipa3_ctx->ipa_wrapper_base, ipa3_ctx->entire_ipa_block_size); if (!ipa3_ctx->reg_collection_base) { Loading drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.h +6 −20 Original line number Diff line number Diff line Loading @@ -314,13 +314,7 @@ struct map_src_dst_addr_s { { GEN_1xVECTOR_REG_OFST(reg_name, 3), \ (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[3].var_name }, \ { GEN_1xVECTOR_REG_OFST(reg_name, 4), \ (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[4].var_name }, \ { GEN_1xVECTOR_REG_OFST(reg_name, 5), \ (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[5].var_name }, \ { GEN_1xVECTOR_REG_OFST(reg_name, 6), \ (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[6].var_name }, \ { GEN_1xVECTOR_REG_OFST(reg_name, 7), \ (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[7].var_name } (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[4].var_name } /* * Macro to define a particular register cfg entry for all resource Loading @@ -330,9 +324,7 @@ struct map_src_dst_addr_s { { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ (u32 *)&ipa_reg_save.ipa.dst_rsrc_grp[0].var_name }, \ { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ (u32 *)&ipa_reg_save.ipa.dst_rsrc_grp[1].var_name }, \ { GEN_1xVECTOR_REG_OFST(reg_name, 2), \ (u32 *)&ipa_reg_save.ipa.dst_rsrc_grp[2].var_name } (u32 *)&ipa_reg_save.ipa.dst_rsrc_grp[1].var_name } /* * Macro to define a particular register cfg entry for all source Loading @@ -348,13 +340,7 @@ struct map_src_dst_addr_s { { GEN_1xVECTOR_REG_OFST(reg_name, 3), \ (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[3].var_name }, \ { GEN_1xVECTOR_REG_OFST(reg_name, 4), \ (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[4].var_name }, \ { GEN_1xVECTOR_REG_OFST(reg_name, 5), \ (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[5].var_name }, \ { GEN_1xVECTOR_REG_OFST(reg_name, 6), \ (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[6].var_name }, \ { GEN_1xVECTOR_REG_OFST(reg_name, 7), \ (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[7].var_name } (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[4].var_name } /* * Macro to define a particular register cfg entry for all dest Loading @@ -364,9 +350,7 @@ struct map_src_dst_addr_s { { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ (u32 *)&ipa_reg_save.ipa.dst_rsrc_cnt[0].var_name }, \ { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ (u32 *)&ipa_reg_save.ipa.dst_rsrc_cnt[1].var_name }, \ { GEN_1xVECTOR_REG_OFST(reg_name, 2), \ (u32 *)&ipa_reg_save.ipa.dst_rsrc_cnt[2].var_name } (u32 *)&ipa_reg_save.ipa.dst_rsrc_cnt[1].var_name } #define IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(reg_name, var_name) \ { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE), \ Loading Loading @@ -969,6 +953,8 @@ static u32 ipa_reg_save_gsi_ch_test_bus_selector_array[] = { * GSI QSB debug bus register save data struct */ struct ipa_reg_save_gsi_test_bus_s { u32 test_bus_selector[ ARRAY_SIZE(ipa_reg_save_gsi_ch_test_bus_selector_array)]; struct gsi_hwio_def_gsi_test_bus_reg_s test_bus_reg[ARRAY_SIZE(ipa_reg_save_gsi_ch_test_bus_selector_array)]; Loading drivers/platform/msm/ipa/ipa_v3/dump/sm8150/ipa_hw_common_ex.h +2 −2 Original line number Diff line number Diff line Loading @@ -105,8 +105,8 @@ #define IPA_HW_DDR_SRC_RSRP_GRP IPA_HW_RSRP_GRP_1 #define IPA_HW_DDR_DEST_RSRP_GRP IPA_HW_RSRP_GRP_1 #define IPA_HW_SRC_RSRP_TYPE_MAX 0x4 #define IPA_HW_DST_RSRP_TYPE_MAX 0x3 #define IPA_HW_SRC_RSRP_TYPE_MAX 0x5 #define IPA_HW_DST_RSRP_TYPE_MAX 0x2 #define GSI_HW_QSB_LOG_MISC_MAX 0x4 Loading Loading
drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.c +6 −1 Original line number Diff line number Diff line Loading @@ -818,9 +818,13 @@ void ipa_save_registers(void) for (i = 0; i < ARRAY_SIZE(ipa_reg_save_gsi_ch_test_bus_selector_array); i++) { ipa_reg_save.gsi.debug.gsi_test_bus.test_bus_selector[i] = ipa_reg_save_gsi_ch_test_bus_selector_array[i]; /* Write test bus selector */ HWIO_GSI_TEST_BUS_SEL_OUT (ipa_reg_save_gsi_ch_test_bus_selector_array[i]); ipa_reg_save.gsi.debug.gsi_test_bus.test_bus_reg[ i].gsi_testbus_reg = (u32)HWIO_GSI_TEST_BUS_REG_IN; Loading Loading @@ -1217,6 +1221,7 @@ static void ipa_hal_save_regs_save_ipa_testbus(void) for (sel_internal = 0; sel_internal <= IPA_TESTBUS_SEL_INTERNAL_PIPE_MAX; sel_internal++) { debug_data_sel.value = 0; debug_data_sel.def.pipe_select = sel_ep; debug_data_sel.def.external_block_select = sel_external; Loading Loading @@ -1269,7 +1274,7 @@ int ipa_reg_save_init(u32 value) ipa3_ctx->ipa_wrapper_base); ipa3_ctx->reg_collection_base = ioremap(ipa3_ctx->ipa_wrapper_base, ioremap_nocache(ipa3_ctx->ipa_wrapper_base, ipa3_ctx->entire_ipa_block_size); if (!ipa3_ctx->reg_collection_base) { Loading
drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.h +6 −20 Original line number Diff line number Diff line Loading @@ -314,13 +314,7 @@ struct map_src_dst_addr_s { { GEN_1xVECTOR_REG_OFST(reg_name, 3), \ (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[3].var_name }, \ { GEN_1xVECTOR_REG_OFST(reg_name, 4), \ (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[4].var_name }, \ { GEN_1xVECTOR_REG_OFST(reg_name, 5), \ (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[5].var_name }, \ { GEN_1xVECTOR_REG_OFST(reg_name, 6), \ (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[6].var_name }, \ { GEN_1xVECTOR_REG_OFST(reg_name, 7), \ (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[7].var_name } (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[4].var_name } /* * Macro to define a particular register cfg entry for all resource Loading @@ -330,9 +324,7 @@ struct map_src_dst_addr_s { { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ (u32 *)&ipa_reg_save.ipa.dst_rsrc_grp[0].var_name }, \ { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ (u32 *)&ipa_reg_save.ipa.dst_rsrc_grp[1].var_name }, \ { GEN_1xVECTOR_REG_OFST(reg_name, 2), \ (u32 *)&ipa_reg_save.ipa.dst_rsrc_grp[2].var_name } (u32 *)&ipa_reg_save.ipa.dst_rsrc_grp[1].var_name } /* * Macro to define a particular register cfg entry for all source Loading @@ -348,13 +340,7 @@ struct map_src_dst_addr_s { { GEN_1xVECTOR_REG_OFST(reg_name, 3), \ (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[3].var_name }, \ { GEN_1xVECTOR_REG_OFST(reg_name, 4), \ (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[4].var_name }, \ { GEN_1xVECTOR_REG_OFST(reg_name, 5), \ (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[5].var_name }, \ { GEN_1xVECTOR_REG_OFST(reg_name, 6), \ (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[6].var_name }, \ { GEN_1xVECTOR_REG_OFST(reg_name, 7), \ (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[7].var_name } (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[4].var_name } /* * Macro to define a particular register cfg entry for all dest Loading @@ -364,9 +350,7 @@ struct map_src_dst_addr_s { { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ (u32 *)&ipa_reg_save.ipa.dst_rsrc_cnt[0].var_name }, \ { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ (u32 *)&ipa_reg_save.ipa.dst_rsrc_cnt[1].var_name }, \ { GEN_1xVECTOR_REG_OFST(reg_name, 2), \ (u32 *)&ipa_reg_save.ipa.dst_rsrc_cnt[2].var_name } (u32 *)&ipa_reg_save.ipa.dst_rsrc_cnt[1].var_name } #define IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(reg_name, var_name) \ { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE), \ Loading Loading @@ -969,6 +953,8 @@ static u32 ipa_reg_save_gsi_ch_test_bus_selector_array[] = { * GSI QSB debug bus register save data struct */ struct ipa_reg_save_gsi_test_bus_s { u32 test_bus_selector[ ARRAY_SIZE(ipa_reg_save_gsi_ch_test_bus_selector_array)]; struct gsi_hwio_def_gsi_test_bus_reg_s test_bus_reg[ARRAY_SIZE(ipa_reg_save_gsi_ch_test_bus_selector_array)]; Loading
drivers/platform/msm/ipa/ipa_v3/dump/sm8150/ipa_hw_common_ex.h +2 −2 Original line number Diff line number Diff line Loading @@ -105,8 +105,8 @@ #define IPA_HW_DDR_SRC_RSRP_GRP IPA_HW_RSRP_GRP_1 #define IPA_HW_DDR_DEST_RSRP_GRP IPA_HW_RSRP_GRP_1 #define IPA_HW_SRC_RSRP_TYPE_MAX 0x4 #define IPA_HW_DST_RSRP_TYPE_MAX 0x3 #define IPA_HW_SRC_RSRP_TYPE_MAX 0x5 #define IPA_HW_DST_RSRP_TYPE_MAX 0x2 #define GSI_HW_QSB_LOG_MISC_MAX 0x4 Loading