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Commit 134d6ab2 authored by Dhaval Patel's avatar Dhaval Patel Committed by Steve Cohen
Browse files

drm/msm/sde: avoid secure flag clear for multirect pipe 



Smart DMA hardware pipe allows secure buffer on rect_0
while non-secure buffer on rect_1 and vice versa. Current
invalid address type programming may clear the buffer type
bits when either rectangle configuration is coming out of
order. For example, rect_0 configures the address type to
secure when it parses buffer configuration. Rect_1 may wipe
out the earlier programming if it is using non-secure buffer.
This patch fixes the address type programming race condition.

Change-Id: Ibf9f2408f55a98339fb977e709dd1ece23cfb784
Signed-off-by: default avatarDhaval Patel <pdhaval@codeaurora.org>
[cohens@codeaurora.org: resolved trivial merge conflict]
Signed-off-by: default avatarSteve Cohen <cohens@codeaurora.org>
parent 9ded59e0

drivers/gpu/drm/msm/msm_smmu.c

+2 −2
Original line number Diff line number Diff line
@@ -249,7 +249,7 @@ static int msm_smmu_map_dma_buf(struct msm_mmu *mmu, struct sg_table *sgt, 
				&sgt->sgl->dma_address, sgt->sgl->dma_length,

				dir, attrs);

		SDE_EVT32(sgt->sgl->dma_address, sgt->sgl->dma_length,

				dir, attrs);

				dir, attrs, client->secure);

	}



	return 0;
@@ -272,7 +272,7 @@ static void msm_smmu_unmap_dma_buf(struct msm_mmu *mmu, struct sg_table *sgt, 
				&sgt->sgl->dma_address, sgt->sgl->dma_length,

				dir);

		SDE_EVT32(sgt->sgl->dma_address, sgt->sgl->dma_length,

				dir);

				dir, client->secure);

	}



	if (!(flags & MSM_BO_EXTBUF))

drivers/gpu/drm/msm/sde/sde_hw_sspp.c

+14 −9
Original line number Diff line number Diff line
@@ -389,7 +389,6 @@ static void sde_hw_sspp_setup_secure(struct sde_hw_pipe *ctx, 


	c = &ctx->hw;



	if (enable) {

	if ((rect_mode == SDE_SSPP_RECT_SOLO)

			|| (rect_mode == SDE_SSPP_RECT_0))

		secure_bit_mask =
@@ -398,10 +397,16 @@ static void sde_hw_sspp_setup_secure(struct sde_hw_pipe *ctx, 
		secure_bit_mask = 0xA;



	secure = SDE_REG_READ(c, SSPP_SRC_ADDR_SW_STATUS + idx);



	if (enable)

		secure |= secure_bit_mask;

	}

	else

		secure &= ~secure_bit_mask;



	SDE_REG_WRITE(c, SSPP_SRC_ADDR_SW_STATUS + idx, secure);



	/* multiple planes share same sw_status register */

	wmb();

}