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Commit 132662f3 authored by Lingutla Chandrasekhar's avatar Lingutla Chandrasekhar
Browse files

ARM: dts: msm: Add energy model for SM6150 



Add energy costs of cpus and clusters for SM6150, which are
used by energy aware scheduler for task placement decision.
Also add cpu's dmips per mhz, which is used as cpu's efficiency.

Change-Id: Ie857c9d58b5d84e13916909f9ae0f8bf03e3bc94
Signed-off-by: default avatarLingutla Chandrasekhar <clingutla@codeaurora.org>
parent 853d7314

arch/arm64/boot/dts/qcom/sm6150.dtsi

+90 −0
Original line number Diff line number Diff line
@@ -52,6 +52,8 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x0>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;

			cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;
@@ -89,6 +91,8 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x100>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;

			cache-size = <0x8000>;

			next-level-cache = <&L2_100>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;
@@ -121,6 +125,8 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x200>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;

			cache-size = <0x8000>;

			next-level-cache = <&L2_200>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;
@@ -152,6 +158,8 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x300>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;

			cache-size = <0x8000>;

			next-level-cache = <&L2_300>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;
@@ -183,6 +191,8 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x400>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;

			cache-size = <0x8000>;

			next-level-cache = <&L2_400>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;
@@ -214,6 +224,8 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x500>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;

			cache-size = <0x8000>;

			next-level-cache = <&L2_500>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;
@@ -245,6 +257,8 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x600>;

			enable-method = "psci";

			capacity-dmips-mhz = <1740>;

			sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;

			cache-size = <0x10000>;

			next-level-cache = <&L2_600>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;
@@ -285,6 +299,8 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x700>;

			enable-method = "psci";

			capacity-dmips-mhz = <1740>;

			sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;

			cache-size = <0x10000>;

			next-level-cache = <&L2_700>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;
@@ -360,6 +376,80 @@ 
		};

	};



	energy_costs: energy-costs {

		compatible = "sched-energy";



		CPU_COST_0: core-cost0 {

			busy-cost-data = <

				576000	25

				748800	31

				1017600	54

				1209600	78

				1363200	105

				1516800	116

				1593600	139

				1804800	178

			>;

			idle-cost-data = <

				16 12 8 6

			>;

		};



		CPU_COST_1: core-cost1 {

			busy-cost-data = <

				652800	236

				768000	273

				979200	446

				1017600	462

				1209600	662

				1363200	894

				1516800	989

				1708800	1276

				1900800	1652

				2112000	2242

				2208000	2713

			>;

			idle-cost-data = <

				100 80 60 40

			>;

		};



		CLUSTER_COST_0: cluster-cost0 {

			busy-cost-data = <

				576000	8

				748800	9

				1017600	12

				1209600	15

				1363200	18

				1516800	21

				1593600	22

				1804800	24

			>;

			idle-cost-data = <

				4 3 2 1

			>;

		};



		CLUSTER_COST_1: cluster-cost1 {

			busy-cost-data = <

				652800	26

				768000	27

				979200	36

				1017600	45

				1209600	55

				1363200	64

				1516800	66

				1708800	72

				1900800	77

				2112000	84

				2208000	90

			>;

			idle-cost-data = <

				4 3 2 1

			>;

		};

	};



	psci {

		compatible = "arm,psci-1.0";

		method = "smc";