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Commit 12d5180b authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms: fix channel_remap setup (v2) 

Most asics just use the hw default value which requires
no explicit programming.  For those that need a different
value, the vbios will program it properly.  As such,
there's no need to program these registers explicitly
in the driver.  Changing MC_SHARED_CHREMAP requires a reload
of all data in vram otherwise its contents will be scambled.

Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=40103



v2: drop now unused channel_remap functions.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarMichel Dänzer <michel.daenzer@amd.com>
Cc: stable@kernel.org
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 02e6859e

drivers/gpu/drm/radeon/evergreen.c

+0 −44
Original line number Original line Diff line number Diff line
@@ -1590,48 +1590,6 @@ static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev, 
	return backend_map;

	return backend_map;

}

}





static void evergreen_program_channel_remap(struct radeon_device *rdev)

{

	u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;



	tmp = RREG32(MC_SHARED_CHMAP);

	switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {

	case 0:

	case 1:

	case 2:

	case 3:

	default:

		/* default mapping */

		mc_shared_chremap = 0x00fac688;

		break;

	}



	switch (rdev->family) {

	case CHIP_HEMLOCK:

	case CHIP_CYPRESS:

	case CHIP_BARTS:

		tcp_chan_steer_lo = 0x54763210;

		tcp_chan_steer_hi = 0x0000ba98;

		break;

	case CHIP_JUNIPER:

	case CHIP_REDWOOD:

	case CHIP_CEDAR:

	case CHIP_PALM:

	case CHIP_SUMO:

	case CHIP_SUMO2:

	case CHIP_TURKS:

	case CHIP_CAICOS:

	default:

		tcp_chan_steer_lo = 0x76543210;

		tcp_chan_steer_hi = 0x0000ba98;

		break;

	}



	WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);

	WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);

	WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);

}



static void evergreen_gpu_init(struct radeon_device *rdev)

static void evergreen_gpu_init(struct radeon_device *rdev)

{

{

	u32 cc_rb_backend_disable = 0;

	u32 cc_rb_backend_disable = 0;
@@ -2078,8 +2036,6 @@ static void evergreen_gpu_init(struct radeon_device *rdev) 
	WREG32(DMIF_ADDR_CONFIG, gb_addr_config);

	WREG32(DMIF_ADDR_CONFIG, gb_addr_config);

	WREG32(HDP_ADDR_CONFIG, gb_addr_config);

	WREG32(HDP_ADDR_CONFIG, gb_addr_config);





	evergreen_program_channel_remap(rdev);



	num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;

	num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;

	grbm_gfx_index = INSTANCE_BROADCAST_WRITES;

	grbm_gfx_index = INSTANCE_BROADCAST_WRITES;

drivers/gpu/drm/radeon/ni.c

+0 −32
Original line number Original line Diff line number Diff line
@@ -569,36 +569,6 @@ static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev, 
	return backend_map;

	return backend_map;

}

}





static void cayman_program_channel_remap(struct radeon_device *rdev)

{

	u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;



	tmp = RREG32(MC_SHARED_CHMAP);

	switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {

	case 0:

	case 1:

	case 2:

	case 3:

	default:

		/* default mapping */

		mc_shared_chremap = 0x00fac688;

		break;

	}



	switch (rdev->family) {

	case CHIP_CAYMAN:

	default:

		//tcp_chan_steer_lo = 0x54763210

		tcp_chan_steer_lo = 0x76543210;

		tcp_chan_steer_hi = 0x0000ba98;

		break;

	}



	WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);

	WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);

	WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);

}



static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev,

static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev,

					    u32 disable_mask_per_se,

					    u32 disable_mask_per_se,

					    u32 max_disable_mask_per_se,

					    u32 max_disable_mask_per_se,
@@ -842,8 +812,6 @@ static void cayman_gpu_init(struct radeon_device *rdev) 
	WREG32(DMIF_ADDR_CONFIG, gb_addr_config);

	WREG32(DMIF_ADDR_CONFIG, gb_addr_config);

	WREG32(HDP_ADDR_CONFIG, gb_addr_config);

	WREG32(HDP_ADDR_CONFIG, gb_addr_config);





	cayman_program_channel_remap(rdev);



	/* primary versions */

	/* primary versions */

	WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);

	WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);

	WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);

	WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);

drivers/gpu/drm/radeon/rv770.c

+0 −51
Original line number Original line Diff line number Diff line
@@ -536,55 +536,6 @@ static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev, 
	return backend_map;

	return backend_map;

}

}





static void rv770_program_channel_remap(struct radeon_device *rdev)

{

	u32 tcp_chan_steer, mc_shared_chremap, tmp;

	bool force_no_swizzle;



	switch (rdev->family) {

	case CHIP_RV770:

	case CHIP_RV730:

		force_no_swizzle = false;

		break;

	case CHIP_RV710:

	case CHIP_RV740:

	default:

		force_no_swizzle = true;

		break;

	}



	tmp = RREG32(MC_SHARED_CHMAP);

	switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {

	case 0:

	case 1:

	default:

		/* default mapping */

		mc_shared_chremap = 0x00fac688;

		break;

	case 2:

	case 3:

		if (force_no_swizzle)

			mc_shared_chremap = 0x00fac688;

		else

			mc_shared_chremap = 0x00bbc298;

		break;

	}



	if (rdev->family == CHIP_RV740)

		tcp_chan_steer = 0x00ef2a60;

	else

		tcp_chan_steer = 0x00fac688;



	/* RV770 CE has special chremap setup */

	if (rdev->pdev->device == 0x944e) {

		tcp_chan_steer = 0x00b08b08;

		mc_shared_chremap = 0x00b08b08;

	}



	WREG32(TCP_CHAN_STEER, tcp_chan_steer);

	WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);

}



static void rv770_gpu_init(struct radeon_device *rdev)

static void rv770_gpu_init(struct radeon_device *rdev)

{

{

	int i, j, num_qd_pipes;

	int i, j, num_qd_pipes;
@@ -785,8 +736,6 @@ static void rv770_gpu_init(struct radeon_device *rdev) 
	WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));

	WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));

	WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));

	WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));





	rv770_program_channel_remap(rdev);



	WREG32(CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);

	WREG32(CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);

	WREG32(CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);

	WREG32(CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);

	WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);

	WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);