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Commit 121920fa authored by Tvrtko Ursulin's avatar Tvrtko Ursulin Committed by Daniel Vetter
Browse files

drm/i915/skl: Query display address through a wrapper 



Need to do this in order to support 90/270 rotated display.

v2: Pass in drm_plane instead of plane index to intel_obj_display_address.

v3:
    * Renamed intel_obj_display_address to intel_plane_obj_offset.
      (Chris Wilson)
    * Simplified rotation check to bitwise AND. (Chris Wilson)

v4:
    * Extracted 90/270 rotation check into a helper function. (Michel Thierry)

v5:
    * Rebased for ggtt view changes.

For: VIZ-4545
Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarMichel Thierry <michel.thierry@intel.com>
Reviewed-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 50470bb0

drivers/gpu/drm/i915/intel_display.c

+17 −6
Original line number Diff line number Diff line
@@ -2301,8 +2301,7 @@ intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, 
	if (!plane_state)

		return 0;



	if (!(plane_state->rotation &

	    (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270))))

	if (!intel_rotation_90_or_270(plane_state->rotation))

		return 0;



	*view = rotated_view;
@@ -2900,6 +2899,17 @@ u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, 
	}

}



unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,

				     struct drm_i915_gem_object *obj)

{

	enum i915_ggtt_view_type view = I915_GGTT_VIEW_NORMAL;



	if (intel_rotation_90_or_270(intel_plane->base.state->rotation))

		view = I915_GGTT_VIEW_ROTATED;



	return i915_gem_obj_ggtt_offset_view(obj, view);

}



static void skylake_update_primary_plane(struct drm_crtc *crtc,

					 struct drm_framebuffer *fb,

					 int x, int y)
@@ -2910,6 +2920,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, 
	struct drm_i915_gem_object *obj;

	int pipe = intel_crtc->pipe;

	u32 plane_ctl, stride_div;

	unsigned long surf_addr;



	if (!intel_crtc->primary_enabled) {

		I915_WRITE(PLANE_CTL(pipe, 0), 0);
@@ -2976,16 +2987,16 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, 
	obj = intel_fb_obj(fb);

	stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],

					       fb->pixel_format);

	surf_addr = intel_plane_obj_offset(to_intel_plane(crtc->primary), obj);



	I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);



	I915_WRITE(PLANE_POS(pipe, 0), 0);

	I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);

	I915_WRITE(PLANE_SIZE(pipe, 0),

		   (intel_crtc->config->pipe_src_h - 1) << 16 |

		   (intel_crtc->config->pipe_src_w - 1));

	I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);

	I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));

	I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);



	POSTING_READ(PLANE_SURF(pipe, 0));

}
@@ -10079,8 +10090,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, 
	if (ret)

		goto cleanup_pending;



	work->gtt_offset =

		i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;

	work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)

						  + intel_crtc->dspaddr_offset;



	if (use_mmio_flip(ring, obj)) {

		ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,

drivers/gpu/drm/i915/intel_drv.h

+9 −0
Original line number Diff line number Diff line
@@ -988,6 +988,12 @@ unsigned int 
intel_tile_height(struct drm_device *dev, uint32_t pixel_format,

		  uint64_t fb_format_modifier);



static inline bool

intel_rotation_90_or_270(unsigned int rotation)

{

	return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));

}



/* shared dpll functions */

struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);

void assert_shared_dpll(struct drm_i915_private *dev_priv,
@@ -1042,6 +1048,9 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode, 
void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);

void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);



unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,

				     struct drm_i915_gem_object *obj);



/* intel_dp.c */

void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);

bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,

drivers/gpu/drm/i915/intel_sprite.c

+4 −1
Original line number Diff line number Diff line
@@ -193,6 +193,7 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, 
	u32 plane_ctl, stride_div;

	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);

	const struct drm_intel_sprite_colorkey *key = &intel_plane->ckey;

	unsigned long surf_addr;



	plane_ctl = PLANE_CTL_ENABLE |

		PLANE_CTL_PIPE_CSC_ENABLE;
@@ -280,12 +281,14 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, 
	else if (key->flags & I915_SET_COLORKEY_SOURCE)

		plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;



	surf_addr = intel_plane_obj_offset(intel_plane, obj);



	I915_WRITE(PLANE_OFFSET(pipe, plane), (y << 16) | x);

	I915_WRITE(PLANE_STRIDE(pipe, plane), fb->pitches[0] / stride_div);

	I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);

	I915_WRITE(PLANE_SIZE(pipe, plane), (crtc_h << 16) | crtc_w);

	I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);

	I915_WRITE(PLANE_SURF(pipe, plane), i915_gem_obj_ggtt_offset(obj));

	I915_WRITE(PLANE_SURF(pipe, plane), surf_addr);

	POSTING_READ(PLANE_SURF(pipe, plane));

}