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Commit 11f5d825 authored by Jayant Shekhar's avatar Jayant Shekhar Committed by Abhijith Desai
Browse files

ARM: dts: msm: add mdss node for qcs405 



Add mdss node and supporting dt files for qcs405
which is used by display framebuffer driver.

Change-Id: Id5380ab67dde7b99b2920eac94e1bc560fd5ad77
Signed-off-by: default avatarJayant Shekhar <jshekhar@codeaurora.org>
Signed-off-by: default avatarNarender Ankam <nankam@codeaurora.org>
Signed-off-by: default avatarAbhijith Desai <desaia@codeaurora.org>
parent 04fcfa38

arch/arm64/boot/dts/qcom/dsi-panel-hx8394d-720p-video.dtsi

0 → 100644
+99 −0
Original line number Diff line number Diff line 
/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



&mdss_mdp {

	dsi_hx8394d_720_vid: qcom,mdss_dsi_hx8394d_720p_video {

		qcom,mdss-dsi-panel-name = "hx8394d 720p video mode dsi panel";

		qcom,mdss-dsi-panel-type = "dsi_video_mode";

		qcom,mdss-dsi-panel-framerate = <60>;

		qcom,mdss-dsi-virtual-channel-id = <0>;

		qcom,mdss-dsi-stream = <0>;

		qcom,mdss-dsi-panel-width = <720>;

		qcom,mdss-dsi-panel-height = <1280>;

		qcom,mdss-dsi-h-front-porch = <52>;

		qcom,mdss-dsi-h-back-porch = <100>;

		qcom,mdss-dsi-h-pulse-width = <24>;

		qcom,mdss-dsi-h-sync-skew = <0>;

		qcom,mdss-dsi-v-back-porch = <20>;

		qcom,mdss-dsi-v-front-porch = <8>;

		qcom,mdss-dsi-v-pulse-width = <4>;

		qcom,mdss-dsi-h-left-border = <0>;

		qcom,mdss-dsi-h-right-border = <0>;

		qcom,mdss-dsi-v-top-border = <0>;

		qcom,mdss-dsi-v-bottom-border = <0>;

		qcom,mdss-dsi-bpp = <24>;

		qcom,mdss-dsi-underflow-color = <0xff>;

		qcom,mdss-dsi-border-color = <0>;

		qcom,mdss-dsi-on-command = [

			39 01 00 00 00 00 04 b9 ff 83 94

			39 01 00 00 00 00 03 ba 33 83

			39 01 00 00 00 00 10 b1 6c 12 12

				37 04 11 f1 80 ec 94 23 80 c0

				d2 18

			39 01 00 00 00 00 0c b2 00 64 0e

				0d 32 23 08 08 1c 4d 00

			39 01 00 00 00 00 0d b4 00 ff 03

				50 03 50 03 50 01 6a 01 6a

			39 01 00 00 00 00 02 bc 07

			39 01 00 00 00 00 04 bf 41 0e 01

			39 01 00 00 00 00 1f d3 00 07 00

				00 00 10 00 32 10 05 00 00 32

				10 00 00 00 32 10 00 00 00 36

				03 09 09 37 00 00 37

			39 01 00 00 00 00 2d d5 02 03 00

				01 06 07 04 05 20 21 22 23 18

				18 18 18 18 18 18 18 18 18 18

				18 18 18 18 18 18 18 18 18 18

				18 18 18 18 18 24 25 18 18 19

				19

			39 01 00 00 00 00 2d d6 05 04 07

				06 01 00 03 02 23 22 21 20 18

				18 18 18 18 18 58 58 18 18 18

				18 18 18 18 18 18 18 18 18 18

				18 18 18 18 18 25 24 19 19 18

				18

			39 01 00 00 00 00 02 cc 09

			39 01 00 00 00 00 03 c0 30 14

			39 01 00 00 00 00 05 c7 00 c0 40 c0

			39 01 00 00 00 00 03 b6 43 43

			05 01 00 00 c8 00 02 11 00

			05 01 00 00 0a 00 02 29 00

			];

		qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00

				05 01 00 00 00 00 02 10 00];

		qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

		qcom,mdss-dsi-off-command-state = "dsi_hs_mode";

		qcom,mdss-dsi-h-sync-pulse = <1>;

		qcom,mdss-dsi-traffic-mode = "burst_mode";

		qcom,mdss-dsi-bllp-eof-power-mode;

		qcom,mdss-dsi-bllp-power-mode;

		qcom,mdss-dsi-lane-0-state;

		qcom,mdss-dsi-lane-1-state;

		qcom,mdss-dsi-lane-2-state;

		qcom,mdss-dsi-lane-3-state;

		qcom,mdss-dsi-panel-timings = [

			79 1a 12 00 3e 42

			16 1e 15 03 04 00

			];

		qcom,mdss-dsi-t-clk-post = <0x04>;

		qcom,mdss-dsi-t-clk-pre = <0x1b>;

		qcom,mdss-dsi-bl-min-level = <1>;

		qcom,mdss-dsi-bl-max-level = <4095>;

		qcom,mdss-dsi-dma-trigger = "trigger_sw";

		qcom,mdss-dsi-mdp-trigger = "none";

		qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";

		qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 20>;

		qcom,mdss-pan-physical-width-dimension = <59>;

		qcom,mdss-pan-physical-height-dimension = <104>;



	};

};

arch/arm64/boot/dts/qcom/qcs405-iot-sku3.dts

+27 −0
Original line number Diff line number Diff line
@@ -15,9 +15,36 @@ 


#include "qcs405.dtsi"

#include "qcs405-nowcd-audio-overlay.dtsi"

#include "qcs405-pinctrl.dtsi"



/ {

	model = "Qualcomm Technologies, Inc. QCS405 sEVB/SLT IOT";

	compatible = "qcom,qcs405-iot", "qcom,qcs405", "qcom,iot";

	qcom,board-id = <0x010020 0x2>;

};

#include "qcs405-mdss-panels.dtsi"



&mdss_mdp {

	qcom,mdss-pref-prim-intf = "dsi";

};



&mdss_dsi {

	hw-config = "single_dsi";

};



&mdss_dsi0 {

	qcom,dsi-pref-prim-pan = <&dsi_hx8394d_720_vid>;

	pinctrl-names = "mdss_default", "mdss_sleep";

	pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;

	pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;



	qcom,platform-te-gpio = <&tlmm 41 0>;

	qcom,platform-reset-gpio = <&tlmm 39 0>;

	qcom,platform-bklight-en-gpio = <&tlmm 48 0>;

};



&dsi_hx8394d_720_vid {

	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_tlmm_gpio";

	qcom,mdss-dsi-bl-pmic-bank-select = <0>;

	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;

};

arch/arm64/boot/dts/qcom/qcs405-iot-sku4.dts

+27 −0
Original line number Diff line number Diff line
@@ -21,3 +21,30 @@ 
	compatible = "qcom,qcs405-iot", "qcom,qcs405", "qcom,iot";

	qcom,board-id = <0x020020 0x1>;

};



#include "qcs405-mdss-panels.dtsi"



&mdss_mdp {

	qcom,mdss-pref-prim-intf = "dsi";

};



&mdss_dsi {

	hw-config = "single_dsi";

};



&mdss_dsi0 {

	qcom,dsi-pref-prim-pan = <&dsi_hx8394d_720_vid>;

	pinctrl-names = "mdss_default", "mdss_sleep";

	pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;

	pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;



	qcom,platform-te-gpio = <&tlmm 41 0>;

	qcom,platform-reset-gpio = <&tlmm 39 0>;

	qcom,platform-bklight-en-gpio = <&tlmm 48 0>;

};



&dsi_hx8394d_720_vid {

	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_tlmm_gpio";

	qcom,mdss-dsi-bl-pmic-bank-select = <0>;

	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;

};

arch/arm64/boot/dts/qcom/qcs405-mdss-panels.dtsi

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+30 −0
Original line number Diff line number Diff line 
/* Copyright (c) 2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#include "dsi-panel-hx8394d-720p-video.dtsi"



&soc {

	dsi_panel_pwr_supply: dsi_panel_pwr_supply {

		#address-cells = <1>;

		#size-cells = <0>;



		qcom,panel-supply-entry@0 {

			reg = <1>;

			qcom,supply-name = "vddio";

			qcom,supply-min-voltage = <1704000>;

			qcom,supply-max-voltage = <1896000>;

			qcom,supply-enable-load = <100000>;

			qcom,supply-disable-load = <100>;

		};



	};

};

arch/arm64/boot/dts/qcom/qcs405-mdss.dtsi

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+332 −0
Original line number Diff line number Diff line 
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#include <dt-bindings/clock/mdss-28nm-pll-clk.h>



&soc {

	mdss_mdp: qcom,mdss_mdp@1a00000 {

		compatible = "qcom,mdss_mdp";

		reg = <0x01a00000 0x90000>,

		      <0x01ab0000 0x1040>;

		reg-names = "mdp_phys", "vbif_phys";

		interrupts = <0 72 0>;

		vdd-supply = <&gdsc_mdss>;



		/* Bus Scale Settings */

		qcom,msm-bus,name = "mdss_mdp";

		qcom,msm-bus,num-cases = <3>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

			<22 512 0 0>,

			<22 512 0 6400000>,

			<22 512 0 6400000>;



		/* Fudge factors */

		qcom,mdss-ab-factor = <1 1>;		/* 1 time  */

		qcom,mdss-ib-factor = <1 1>;		/* 1 time  */

		qcom,mdss-clk-factor = <105 100>;	/* 1.05 times */



		qcom,max-mixer-width = <2048>;

		qcom,max-pipe-width = <2048>;



		/* VBIF QoS remapper settings*/

		qcom,mdss-vbif-qos-rt-setting = <1 2 2 2>;

		qcom,mdss-vbif-qos-nrt-setting = <1 1 1 1>;



		qcom,mdss-has-panic-ctrl;

		qcom,mdss-per-pipe-panic-luts = <0x000f>,

						<0x0>,

						<0xfffc>,

						<0x0>;



		qcom,mdss-mdp-reg-offset = <0x00001000>;

		qcom,max-bandwidth-low-kbps = <1800000>;

		qcom,max-bandwidth-high-kbps = <1800000>;

		qcom,max-bandwidth-per-pipe-kbps = <1000000>;



		/* Bandwidth limit settings */

		qcom,max-bw-settings = <1 3100000>,	/* Default */

				       <2 1700000>;	/* Camera */



		qcom,max-clk-rate = <320000000>;

		qcom,mdss-default-ot-rd-limit = <32>;

		qcom,mdss-default-ot-wr-limit = <16>;



		qcom,mdss-pipe-vig-off = <0x00005000>;

		qcom,mdss-pipe-rgb-off = <0x00015000 0x00017000>;

		qcom,mdss-pipe-dma-off = <0x00025000>;

		qcom,mdss-pipe-cursor-off = <0x00035000>;



		qcom,mdss-pipe-vig-xin-id = <0>;

		qcom,mdss-pipe-rgb-xin-id = <1 5>;

		qcom,mdss-pipe-dma-xin-id = <2>;

		qcom,mdss-pipe-cursor-xin-id = <7>;



		/* Offsets relative to "mdp_phys + mdp-reg-offset" address */

		qcom,mdss-pipe-vig-clk-ctrl-offsets = <0x2AC 0 0>;

		qcom,mdss-pipe-rgb-clk-ctrl-offsets = <0x2AC 4 8>,

						      <0x2B4 4 8>;

		qcom,mdss-pipe-dma-clk-ctrl-offsets = <0x2AC 8 12>;

		qcom,mdss-pipe-cursor-clk-ctrl-offsets = <0x3A8 16 15>;





		qcom,mdss-ctl-off = <0x00002000 0x00002200 0x00002400

						0x00002600 0x00002800>;

		qcom,mdss-mixer-intf-off = <0x00045000 0x00046000>;

		qcom,mdss-dspp-off = <0x00055000>;

		qcom,mdss-wb-off = <0x00066000>;

		qcom,mdss-intf-off = <0x00000000 0x0006B800

						0x00000000 0x0006C800>;

		qcom,mdss-pingpong-off = <0x00071000 0x00071800>;

		qcom,mdss-wfd-mode = "intf";

		qcom,mdss-has-decimation;

		qcom,mdss-has-non-scalar-rgb;

		qcom,mdss-has-rotator-downscale;

		qcom,mdss-rot-downscale-min = <2>;

		qcom,mdss-rot-downscale-max = <16>;

		qcom,mdss-idle-power-collapse-enabled;

		qcom,mdss-rot-block-size = <64>;



		clocks = <&clock_gcc GCC_MDSS_AHB_CLK>,

			 <&clock_gcc GCC_MDSS_AXI_CLK>,

			 <&clock_gcc GCC_MDSS_MDP_CLK>,

			 <&clock_gcc_mdss MDSS_MDP_VOTE_CLK>,

			 <&clock_gcc GCC_MDSS_VSYNC_CLK>,

			 <&clock_gcc GCC_BIMC_MDSS_CLK>;

		clock-names = "iface_clk", "bus_clk", "core_clk_src",

				"core_clk", "vsync_clk", "bimc_clk";



		qcom,mdp-settings = <0x0506c 0x00000000>,

				    <0x1506c 0x00000000>,

				    <0x1706c 0x00000000>,

				    <0x2506c 0x00000000>;



		qcom,regs-dump-mdp = <0x01000 0x01454>,

				     <0x02000 0x02064>,

				     <0x02200 0x02264>,

				     <0x02400 0x02464>,

				     <0x05000 0x05150>,

				     <0x05200 0x05230>,

				     <0x15000 0x15150>,

				     <0x17000 0x17150>,

				     <0x25000 0x25150>,

				     <0x35000 0x35150>,

				     <0x45000 0x452bc>,

				     <0x46000 0x462bc>,

				     <0x55000 0x5522c>,

				     <0x65000 0x652c0>,

				     <0x66000 0x662c0>,

				     <0x6b800 0x6ba68>,

				     <0x6c800 0x6c268>,

				     <0x71000 0x710d4>,

				     <0x71800 0x718d4>;



		qcom,regs-dump-names-mdp = "MDP",

			"CTL_0",    "CTL_1", "CTL_2",

			"VIG0_SSPP", "VIG0",

			"RGB0_SSPP", "RGB1_SSPP",

			"DMA0_SSPP",

			"CURSOR0_SSPP",

			"LAYER_0", "LAYER_1",

			"DSPP_0",

			"WB_0",    "WB_2",

			"INTF_1",  "INTF_3",

			"PP_0",    "PP_1";



		/* buffer parameters to calculate prefill bandwidth */

		qcom,mdss-prefill-outstanding-buffer-bytes = <0>;

		qcom,mdss-prefill-y-buffer-bytes = <0>;

		qcom,mdss-prefill-scaler-buffer-lines-bilinear = <2>;

		qcom,mdss-prefill-scaler-buffer-lines-caf = <4>;

		qcom,mdss-prefill-post-scaler-buffer-pixels = <2048>;

		qcom,mdss-prefill-pingpong-buffer-pixels = <4096>;



		qcom,mdss-pp-offsets {

			qcom,mdss-sspp-mdss-igc-lut-off = <0x2000>;

			qcom,mdss-sspp-vig-pcc-off = <0x1780>;

			qcom,mdss-sspp-rgb-pcc-off = <0x380>;

			qcom,mdss-sspp-dma-pcc-off = <0x380>;

			qcom,mdss-lm-pgc-off = <0x3C0>;

			qcom,mdss-dspp-pcc-off = <0x1700>;

			qcom,mdss-dspp-pgc-off = <0x17C0>;

		};



		qcom,mdss-reg-bus {

			/* Reg Bus Scale Settings */

			qcom,msm-bus,name = "mdss_reg";

			qcom,msm-bus,num-cases = <4>;

			qcom,msm-bus,num-paths = <1>;

			qcom,msm-bus,active-only;

			qcom,msm-bus,vectors-KBps =

				<1 590 0 0>,

				<1 590 0 76800>,

				<1 590 0 160000>,

				<1 590 0 320000>;

		};



		qcom,mdss-hw-rt-bus {

			/* Bus Scale Settings */

			qcom,msm-bus,name = "mdss_hw_rt";

			qcom,msm-bus,num-cases = <2>;

			qcom,msm-bus,num-paths = <1>;

			qcom,msm-bus,vectors-KBps =

				<22 512 0 0>,

				<22 512 0 1000>;

		};



		smmu_mdp_unsec: qcom,smmu_mdp_unsec_cb {

			compatible = "qcom,smmu_mdp_unsec";

			iommus = <&apps_smmu 0xC00 0>; /* For NS ctx bank */

		};



		mdss_fb0: qcom,mdss_fb_primary {

			cell-index = <0>;

			compatible = "qcom,mdss-fb";

		};



		mdss_fb1: qcom,mdss_fb_wfd {

			cell-index = <1>;

			compatible = "qcom,mdss-fb";

		};



		mdss_fb2: qcom,mdss_fb_secondary {

			cell-index = <2>;

			compatible = "qcom,mdss-fb";

		};

	};



	mdss_dsi: qcom,mdss_dsi@0 {

		compatible = "qcom,mdss-dsi";

		hw-config = "single_dsi";

		#address-cells = <1>;

		#size-cells = <1>;

		gdsc-supply = <&gdsc_mdss>;

		vdda-1p2-supply = <&pms405_l4>;

		vdda-1p8-supply = <&pms405_l5>;



		/* Bus Scale Settings */

		qcom,msm-bus,name = "mdss_dsi";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

			<22 512 0 0>,

			<22 512 0 1000>;



		ranges = <0x1a94000 0x1a94000 0x300

			0x1a94400 0x1a94400 0x280

			0x1a94b80 0x1a94b80 0x30

			0x193e000 0x193e000 0x30

			0x1a96000 0x1a96000 0x300

			0x1a96400 0x1a96400 0x280

			0x1a96b80 0x1a96b80 0x30

			0x193e000 0x193e000 0x30>;



		clocks = <&clock_gcc_mdss MDSS_MDP_VOTE_CLK>,

			 <&clock_gcc GCC_MDSS_AHB_CLK>,

			<&clock_gcc GCC_MDSS_AXI_CLK>,

			<&mdss_dsi0_pll BYTECLK_SRC_0_CLK>,

			<&mdss_dsi0_pll PCLK_SRC_0_CLK>;

		clock-names = "mdp_core_clk", "iface_clk", "bus_clk",

			"ext_byte0_clk", "ext_pixel0_clk";



		qcom,mmss-ulp-clamp-ctrl-offset = <0x20>;

		qcom,mmss-phyreset-ctrl-offset = <0x24>;



		qcom,mdss-fb-map-prim = <&mdss_fb0>;

		qcom,mdss-fb-map-sec = <&mdss_fb2>;

		/*qcom,mdss-fb-map = <&mdss_fb0>;*/

		qcom,core-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,core-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "gdsc";

				qcom,supply-min-voltage = <0>;

				qcom,supply-max-voltage = <0>;

				qcom,supply-enable-load = <0>;

				qcom,supply-disable-load = <0>;

			};

		};



		qcom,ctrl-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,ctrl-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "vdda-1p2";

				qcom,supply-min-voltage = <1200000>;

				qcom,supply-max-voltage = <1200000>;

				qcom,supply-enable-load = <100000>;

				qcom,supply-disable-load = <100>;

				qcom,supply-post-on-sleep = <20>;

			};

		};



		qcom,phy-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,phy-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "vdda-1p8";

				qcom,supply-min-voltage = <1800000>;

				qcom,supply-max-voltage = <1800000>;

				qcom,supply-enable-load = <100000>;

				qcom,supply-disable-load = <100>;

			};

		};



		mdss_dsi0: qcom,mdss_dsi_ctrl0@1a94000 {

			compatible = "qcom,mdss-dsi-ctrl";

			label = "MDSS DSI CTRL->0";

			cell-index = <0>;

			reg = <0x1a94000 0x300>,

				<0x1a94400 0x280>,

				<0x1a94b80 0x30>,

				<0x193e000 0x30>;

			reg-names = "dsi_ctrl", "dsi_phy",

			      "dsi_phy_regulator", "mmss_misc_phys";



			qcom,timing-db-mode;

			qcom,mdss-mdp = <&mdss_mdp>;

			vddio-supply = <&pms405_l6>;



			clocks = <&clock_gcc_mdss GCC_MDSS_BYTE0_CLK>,

				<&clock_gcc_mdss GCC_MDSS_PCLK0_CLK>,

				<&clock_gcc GCC_MDSS_ESC0_CLK>,

				<&clock_gcc_mdss BYTE0_CLK_SRC>,

				<&clock_gcc_mdss PCLK0_CLK_SRC>;

			clock-names = "byte_clk", "pixel_clk", "core_clk",

				"byte_clk_rcg", "pixel_clk_rcg";



			qcom,platform-strength-ctrl = [ff 06];

			qcom,platform-bist-ctrl = [00 00 b1 ff 00 00];

			qcom,platform-regulator-settings = [03 08 07 00

				20 07 01];

			qcom,platform-lane-config = [01 c0 00 00 00 00 00 01 97

				01 c0 00 00 05 00 00 01 97

				01 c0 00 00 0a 00 00 01 97

				01 c0 00 00 0f 00 00 01 97

				00 40 00 00 00 00 00 01 ff];

		};

	};



	qcom,mdss_wb_panel {

		compatible = "qcom,mdss_wb";

		qcom,mdss_pan_res = <640 640>;

		qcom,mdss_pan_bpp = <24>;

		qcom,mdss-fb-map = <&mdss_fb1>;

	};



};