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Commit 11519948 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: gpucc-sm8150: Remove control of the GPU ACD clocks"

parents 0a4a45a1 2ee8b1e2

drivers/clk/qcom/gpucc-sm8150.c

+0 −29
Original line number Diff line number Diff line
@@ -143,32 +143,6 @@ static struct clk_rcg2 gpu_cc_gmu_clk_src = { 
	},

};



static struct clk_branch gpu_cc_acd_ahb_clk = {

	.halt_reg = 0x1168,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x1168,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gpu_cc_acd_ahb_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gpu_cc_acd_cxo_clk = {

	.halt_reg = 0x1164,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x1164,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gpu_cc_acd_cxo_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gpu_cc_ahb_clk = {

	.halt_reg = 0x1078,

	.halt_check = BRANCH_HALT,
@@ -411,8 +385,6 @@ struct clk_hw *gpu_cc_sm8150_hws[] = { 
};



static struct clk_regmap *gpu_cc_sm8150_clocks[] = {

	[GPU_CC_ACD_AHB_CLK] = &gpu_cc_acd_ahb_clk.clkr,

	[GPU_CC_ACD_CXO_CLK] = &gpu_cc_acd_cxo_clk.clkr,

	[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,

	[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,

	[GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr,
@@ -433,7 +405,6 @@ static struct clk_regmap *gpu_cc_sm8150_clocks[] = { 
};



static const struct qcom_reset_map gpu_cc_sm8150_resets[] = {

	[GPUCC_GPU_CC_ACD_BCR] = { 0x1160 },

	[GPUCC_GPU_CC_CX_BCR] = { 0x1068 },

	[GPUCC_GPU_CC_GMU_BCR] = { 0x111c },

	[GPUCC_GPU_CC_GX_BCR] = { 0x1008 },

include/dt-bindings/clock/qcom,gpucc-sm8150.h

+23 −26
Original line number Diff line number Diff line
@@ -15,34 +15,31 @@ 
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8150_H



/* GPUCC clock registers */

#define GPU_CC_ACD_AHB_CLK					0

#define GPU_CC_ACD_CXO_CLK					1

#define GPU_CC_AHB_CLK						2

#define GPU_CC_CRC_AHB_CLK					3

#define GPU_CC_CX_APB_CLK					4

#define GPU_CC_CX_GMU_CLK					5

#define GPU_CC_CX_QDSS_AT_CLK					6

#define GPU_CC_CX_QDSS_TRIG_CLK					7

#define GPU_CC_CX_QDSS_TSCTR_CLK				8

#define GPU_CC_CX_SNOC_DVM_CLK					9

#define GPU_CC_CXO_AON_CLK					10

#define GPU_CC_CXO_CLK						11

#define GPU_CC_GMU_CLK_SRC					12

#define GPU_CC_GX_GMU_CLK					13

#define GPU_CC_GX_QDSS_TSCTR_CLK				14

#define GPU_CC_GX_VSENSE_CLK					15

#define GPU_CC_PLL1						16

#define GPU_CC_PLL_TEST_CLK					17

#define GPU_CC_SLEEP_CLK					18

#define GPU_CC_AHB_CLK						0

#define GPU_CC_CRC_AHB_CLK					1

#define GPU_CC_CX_APB_CLK					2

#define GPU_CC_CX_GMU_CLK					3

#define GPU_CC_CX_QDSS_AT_CLK					4

#define GPU_CC_CX_QDSS_TRIG_CLK					5

#define GPU_CC_CX_QDSS_TSCTR_CLK				6

#define GPU_CC_CX_SNOC_DVM_CLK					7

#define GPU_CC_CXO_AON_CLK					8

#define GPU_CC_CXO_CLK						9

#define GPU_CC_GMU_CLK_SRC					10

#define GPU_CC_GX_GMU_CLK					11

#define GPU_CC_GX_QDSS_TSCTR_CLK				12

#define GPU_CC_GX_VSENSE_CLK					13

#define GPU_CC_PLL1						14

#define GPU_CC_PLL_TEST_CLK					15

#define GPU_CC_SLEEP_CLK					16



/* GPUCC reset clock registers */

#define GPUCC_GPU_CC_ACD_BCR					0

#define GPUCC_GPU_CC_CX_BCR					1

#define GPUCC_GPU_CC_GFX3D_AON_BCR				2

#define GPUCC_GPU_CC_GMU_BCR					3

#define GPUCC_GPU_CC_GX_BCR					4

#define GPUCC_GPU_CC_SPDM_BCR					5

#define GPUCC_GPU_CC_XO_BCR					6

#define GPUCC_GPU_CC_CX_BCR					0

#define GPUCC_GPU_CC_GFX3D_AON_BCR				1

#define GPUCC_GPU_CC_GMU_BCR					2

#define GPUCC_GPU_CC_GX_BCR					3

#define GPUCC_GPU_CC_SPDM_BCR					4

#define GPUCC_GPU_CC_XO_BCR					5



/* Dummy clocks for rate measurement */

#define MEASURE_ONLY_GPU_CC_CX_GFX3D_CLK		0