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Commit 1082150a authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: enable dynamic clk switch feature for sdmmagpie"

parents 58ac266f 7222a0a5

arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi

+14 −3
Original line number Original line Diff line number Diff line
@@ -104,7 +104,9 @@ 




		qcom,dsi-ctrl-num = <0>;

		qcom,dsi-ctrl-num = <0>;

		qcom,dsi-phy-num = <0>;

		qcom,dsi-phy-num = <0>;

		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",

			"src_byte_clk0", "src_pixel_clk0",

			"shadow_byte_clk0", "shadow_pixel_clk0";





		qcom,dsi-panel = <&dsi_sw43404_amoled_video>;

		qcom,dsi-panel = <&dsi_sw43404_amoled_video>;

	};

	};
@@ -294,9 +296,15 @@ 
		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			 <&mdss_dsi0_pll PCLK_MUX_0_CLK>,

			 <&mdss_dsi0_pll PCLK_MUX_0_CLK>,

			 <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,

			 <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,

			 <&mdss_dsi1_pll PCLK_MUX_1_CLK>;

			 <&mdss_dsi1_pll PCLK_MUX_1_CLK>,

			 <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>,

			 <&mdss_dsi0_pll PCLK_SRC_0_CLK>,

			 <&mdss_dsi0_pll SHADOW_BYTECLK_SRC_0_CLK>,

			 <&mdss_dsi0_pll SHADOW_PCLK_SRC_0_CLK>;

		clock-names = "mux_byte_clk0", "mux_pixel_clk0",

		clock-names = "mux_byte_clk0", "mux_pixel_clk0",

				"mux_byte_clk1", "mux_pixel_clk1";

				"mux_byte_clk1", "mux_pixel_clk1",

				"src_byte_clk0", "src_pixel_clk0",

				"shadow_byte_clk0", "shadow_pixel_clk0";





		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_te_active &disp_pins_default>;

		pinctrl-0 = <&sde_te_active &disp_pins_default>;
@@ -389,6 +397,9 @@ 
	qcom,dsi-supported-dfps-list = <60 57 55>;

	qcom,dsi-supported-dfps-list = <60 57 55>;

	qcom,mdss-dsi-pan-enable-dynamic-fps;

	qcom,mdss-dsi-pan-enable-dynamic-fps;

	qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_hfp";

	qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_hfp";

	qcom,dsi-dyn-clk-enable;

	qcom,dsi-dyn-clk-list =

		<534712320 532484352 530256384 525800448 528028416>;

	qcom,mdss-dsi-display-timings {

	qcom,mdss-dsi-display-timings {

		timing@0{

		timing@0{

			qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 1F 1E 05

			qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 1F 1E 05

arch/arm64/boot/dts/qcom/sdmmagpie-sde-pll.dtsi

+10 −5
Original line number Original line Diff line number Diff line 
/* Copyright (c) 2018, The Linux Foundation. All rights reserved.

/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 *

 *

 * This program is free software; you can redistribute it and/or modify

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * it under the terms of the GNU General Public License version 2 and
@@ -18,11 +18,14 @@ 
		#clock-cells = <1>;

		#clock-cells = <1>;

		reg = <0xae94a00 0x1e0>,

		reg = <0xae94a00 0x1e0>,

		      <0xae94400 0x800>,

		      <0xae94400 0x800>,

		      <0xaf03000 0x8>;

		      <0xaf03000 0x8>,

		reg-names = "pll_base", "phy_base", "gdsc_base";

		      <0xae94200 0x100>;

		reg-names = "pll_base", "phy_base", "gdsc_base",

			"dynamic_pll_base";

		clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>;

		clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>;

		clock-names = "iface_clk";

		clock-names = "iface_clk";

		clock-rate = <0>;

		clock-rate = <0>;

		memory-region = <&dfps_data_memory>;

		gdsc-supply = <&mdss_core_gdsc>;

		gdsc-supply = <&mdss_core_gdsc>;

		qcom,platform-supply-entries {

		qcom,platform-supply-entries {

			#address-cells = <1>;

			#address-cells = <1>;
@@ -45,8 +48,10 @@ 
		#clock-cells = <1>;

		#clock-cells = <1>;

		reg = <0xae96a00 0x1e0>,

		reg = <0xae96a00 0x1e0>,

		      <0xae96400 0x800>,

		      <0xae96400 0x800>,

		      <0xaf03000 0x8>;

		      <0xaf03000 0x8>,

		reg-names = "pll_base", "phy_base", "gdsc_base";

		      <0xae96200 0x100>;

		reg-names = "pll_base", "phy_base", "gdsc_base",

			"dynamic_pll_base";

		clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>;

		clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>;

		clock-names = "iface_clk";

		clock-names = "iface_clk";

		clock-rate = <0>;

		clock-rate = <0>;

arch/arm64/boot/dts/qcom/sdmmagpie-sde.dtsi

+7 −5
Original line number Original line Diff line number Diff line 
/* Copyright (c) 2018, The Linux Foundation. All rights reserved.

/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 *

 *

 * This program is free software; you can redistribute it and/or modify

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * it under the terms of the GNU General Public License version 2 and
@@ -503,8 +503,9 @@ 
		compatible = "qcom,dsi-phy-v3.0";

		compatible = "qcom,dsi-phy-v3.0";

		label = "dsi-phy-0";

		label = "dsi-phy-0";

		cell-index = <0>;

		cell-index = <0>;

		reg = <0xae94400 0x7c0>;

		reg = <0xae94400 0x7c0>,

		reg-names = "dsi_phy";

		    <0xae94200 0x100>;

		reg-names = "dsi_phy", "dyn_refresh_base";

		vdda-0p9-supply = <&pm6150_l4>;

		vdda-0p9-supply = <&pm6150_l4>;

		qcom,platform-strength-ctrl = [55 03

		qcom,platform-strength-ctrl = [55 03

						55 03

						55 03
@@ -535,8 +536,9 @@ 
		compatible = "qcom,dsi-phy-v3.0";

		compatible = "qcom,dsi-phy-v3.0";

		label = "dsi-phy-1";

		label = "dsi-phy-1";

		cell-index = <1>;

		cell-index = <1>;

		reg = <0xae96400 0x7c0>;

		reg = <0xae96400 0x7c0>,

		reg-names = "dsi_phy";

		    <0xae96200 0x100>;

		reg-names = "dsi_phy", "dyn_refresh_base";

		vdda-0p9-supply = <&pm6150_l4>;

		vdda-0p9-supply = <&pm6150_l4>;

		qcom,platform-strength-ctrl = [55 03

		qcom,platform-strength-ctrl = [55 03

						55 03

						55 03

arch/arm64/boot/dts/qcom/sdmmagpie.dtsi

+7 −2
Original line number Original line Diff line number Diff line 
/* Copyright (c) 2018, The Linux Foundation. All rights reserved.

/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 *

 *

 * This program is free software; you can redistribute it and/or modify

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * it under the terms of the GNU General Public License version 2 and
@@ -650,10 +650,15 @@ 
		};

		};





		cont_splash_memory: cont_splash_region@9c000000 {

		cont_splash_memory: cont_splash_region@9c000000 {

			reg = <0x0 0x9c000000 0x0 0x02400000>;

			reg = <0x0 0x9c000000 0x0 0x02300000>;

			label = "cont_splash_region";

			label = "cont_splash_region";

		};

		};





		dfps_data_memory: dfps_data_region@9e300000 {

			reg = <0x0 0x9e300000 0x0 0x0100000>;

			label = "dfps_data_region";

		};



		dump_mem: mem_dump_region {

		dump_mem: mem_dump_region {

			compatible = "shared-dma-pool";

			compatible = "shared-dma-pool";

			reusable;

			reusable;