Loading arch/arm64/boot/dts/qcom/sdm855-coresight.dtsi +10 −10 Original line number Diff line number Diff line Loading @@ -1599,7 +1599,7 @@ reg = <0x78e0000 0x1000>; reg-names = "cti-base"; coresight-name = "coresight-cti-APSS_CTI0"; coresight-name = "coresight-cti-apss_cti0"; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; Loading @@ -1611,7 +1611,7 @@ reg = <0x78f0000 0x1000>; reg-names = "cti-base"; coresight-name = "coresight-cti-APSS_CTI1"; coresight-name = "coresight-cti-apss_cti1"; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; Loading @@ -1623,7 +1623,7 @@ reg = <0x7900000 0x1000>; reg-names = "cti-base"; coresight-name = "coresight-cti-APSS_CTI2"; coresight-name = "coresight-cti-apss_cti2"; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; Loading @@ -1635,7 +1635,7 @@ reg = <0x6a02000 0x1000>; reg-names = "cti-base"; coresight-name = "coresight-cti-DDR_DL_0_CTI0"; coresight-name = "coresight-cti-ddr_dl_0_cti0"; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; Loading @@ -1647,7 +1647,7 @@ reg = <0x6a03000 0x1000>; reg-names = "cti-base"; coresight-name = "coresight-cti-DDR_DL_0_CTI1"; coresight-name = "coresight-cti-ddr_dl_0_cti1"; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; Loading @@ -1659,7 +1659,7 @@ reg = <0x6a10000 0x1000>; reg-names = "cti-base"; coresight-name = "coresight-cti-DDR_DL_1_CTI0"; coresight-name = "coresight-cti-ddr_dl_1_cti0"; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; Loading @@ -1671,7 +1671,7 @@ reg = <0x6a11000 0x1000>; reg-names = "cti-base"; coresight-name = "coresight-cti-DDR_DL_1_CTI1"; coresight-name = "coresight-cti-ddr_dl_1_cti1"; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; Loading @@ -1683,7 +1683,7 @@ reg = <0x6c09000 0x1000>; reg-names = "cti-base"; coresight-name = "coresight-cti-DLMM_CTI0"; coresight-name = "coresight-cti-dlmm_cti0"; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; Loading @@ -1695,7 +1695,7 @@ reg = <0x6c0a000 0x1000>; reg-names = "cti-base"; coresight-name = "coresight-cti-DLMM_CTI1"; coresight-name = "coresight-cti-dlmm_cti1"; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; Loading Loading @@ -2020,7 +2020,7 @@ reg = <0x6b04000 0x1000>; reg-names = "cti-base"; coresight-name = "coresight-cti-SWAO_CTI0"; coresight-name = "coresight-cti-swao_cti0"; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; Loading Loading
arch/arm64/boot/dts/qcom/sdm855-coresight.dtsi +10 −10 Original line number Diff line number Diff line Loading @@ -1599,7 +1599,7 @@ reg = <0x78e0000 0x1000>; reg-names = "cti-base"; coresight-name = "coresight-cti-APSS_CTI0"; coresight-name = "coresight-cti-apss_cti0"; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; Loading @@ -1611,7 +1611,7 @@ reg = <0x78f0000 0x1000>; reg-names = "cti-base"; coresight-name = "coresight-cti-APSS_CTI1"; coresight-name = "coresight-cti-apss_cti1"; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; Loading @@ -1623,7 +1623,7 @@ reg = <0x7900000 0x1000>; reg-names = "cti-base"; coresight-name = "coresight-cti-APSS_CTI2"; coresight-name = "coresight-cti-apss_cti2"; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; Loading @@ -1635,7 +1635,7 @@ reg = <0x6a02000 0x1000>; reg-names = "cti-base"; coresight-name = "coresight-cti-DDR_DL_0_CTI0"; coresight-name = "coresight-cti-ddr_dl_0_cti0"; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; Loading @@ -1647,7 +1647,7 @@ reg = <0x6a03000 0x1000>; reg-names = "cti-base"; coresight-name = "coresight-cti-DDR_DL_0_CTI1"; coresight-name = "coresight-cti-ddr_dl_0_cti1"; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; Loading @@ -1659,7 +1659,7 @@ reg = <0x6a10000 0x1000>; reg-names = "cti-base"; coresight-name = "coresight-cti-DDR_DL_1_CTI0"; coresight-name = "coresight-cti-ddr_dl_1_cti0"; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; Loading @@ -1671,7 +1671,7 @@ reg = <0x6a11000 0x1000>; reg-names = "cti-base"; coresight-name = "coresight-cti-DDR_DL_1_CTI1"; coresight-name = "coresight-cti-ddr_dl_1_cti1"; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; Loading @@ -1683,7 +1683,7 @@ reg = <0x6c09000 0x1000>; reg-names = "cti-base"; coresight-name = "coresight-cti-DLMM_CTI0"; coresight-name = "coresight-cti-dlmm_cti0"; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; Loading @@ -1695,7 +1695,7 @@ reg = <0x6c0a000 0x1000>; reg-names = "cti-base"; coresight-name = "coresight-cti-DLMM_CTI1"; coresight-name = "coresight-cti-dlmm_cti1"; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; Loading Loading @@ -2020,7 +2020,7 @@ reg = <0x6b04000 0x1000>; reg-names = "cti-base"; coresight-name = "coresight-cti-SWAO_CTI0"; coresight-name = "coresight-cti-swao_cti0"; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; Loading