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Commit 0fa9505e authored by Zhenhua Huang's avatar Zhenhua Huang
Browse files

ARM: dts: qcom: Add iommu bus voting details for atoll 



Add iommu bus voting details to vote for the bus clock rate required
to access iommu registers on atoll.

Change-Id: Ib6a526b52145ab4758d007aa6680024e6aac75dd
Signed-off-by: default avatarZhenhua Huang <zhenhuah@codeaurora.org>
parent 71307250

arch/arm64/boot/dts/qcom/msm-arm-smmu-atoll.dtsi

+67 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ 
 * GNU General Public License for more details.

 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/msm/msm-bus-ids.h>



&soc {

	kgsl_smmu: arm,smmu-kgsl@5040000 {
@@ -138,6 +139,17 @@ 
				<0x15182200 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x0 0x400>;

			qcom,msm-bus,name = "apps_smmu";

			qcom,msm-bus,num-cases = <2>;

			qcom,msm-bus,active-only;

			qcom,msm-bus,num-paths = <1>;

			qcom,msm-bus,vectors-KBps =

				<MSM_BUS_MASTER_GEM_NOC_SNOC>,

				<MSM_BUS_SLAVE_IMEM_CFG>,

				<0 0>,

				<MSM_BUS_MASTER_GEM_NOC_SNOC>,

				<MSM_BUS_SLAVE_IMEM_CFG>,

				<0 1000>;

		};



		anoc_2_tbu: anoc_2_tbu@0x15189000 {
@@ -146,6 +158,17 @@ 
				<0x15182208 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x400 0x400>;

			qcom,msm-bus,name = "apps_smmu";

			qcom,msm-bus,num-cases = <2>;

			qcom,msm-bus,active-only;

			qcom,msm-bus,num-paths = <1>;

			qcom,msm-bus,vectors-KBps =

				<MSM_BUS_MASTER_GEM_NOC_SNOC>,

				<MSM_BUS_SLAVE_IMEM_CFG>,

				<0 0>,

				<MSM_BUS_MASTER_GEM_NOC_SNOC>,

				<MSM_BUS_SLAVE_IMEM_CFG>,

				<0 1000>;

		};



		mnoc_hf_0_tbu: mnoc_hf_0_tbu@0x1518d000 {
@@ -156,6 +179,17 @@ 
			qcom,stream-id-range = <0x800 0x400>;

			qcom,regulator-names = "vdd";

			vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>;

			qcom,msm-bus,name = "mnoc_hf_0_tbu";

			qcom,msm-bus,num-cases = <2>;

			qcom,msm-bus,active-only;

			qcom,msm-bus,num-paths = <1>;

			qcom,msm-bus,vectors-KBps =

				<MSM_BUS_MASTER_MDP_PORT0>,

				<MSM_BUS_SLAVE_MNOC_HF_MEM_NOC>,

				<0 0>,

				<MSM_BUS_MASTER_MDP_PORT0>,

				<MSM_BUS_SLAVE_MNOC_HF_MEM_NOC>,

				<0 1000>;

		};



		mnoc_sf_0_tbu: mnoc_sf_0_tbu@0x15191000 {
@@ -166,6 +200,17 @@ 
			qcom,stream-id-range = <0xc00 0x400>;

			qcom,regulator-names = "vdd";

			vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc>;

			qcom,msm-bus,name = "mnoc_sf_0_tbu";

			qcom,msm-bus,num-cases = <2>;

			qcom,msm-bus,active-only;

			qcom,msm-bus,num-paths = <1>;

			qcom,msm-bus,vectors-KBps =

				<MSM_BUS_MASTER_CAMNOC_SF>,

				<MSM_BUS_SLAVE_MNOC_SF_MEM_NOC>,

				<0 0>,

				<MSM_BUS_MASTER_CAMNOC_SF>,

				<MSM_BUS_SLAVE_MNOC_SF_MEM_NOC>,

				<0 1000>;

		};



		lpass_noc_tbu: lpass_noc_tbu@0x15195000 {
@@ -174,6 +219,17 @@ 
				<0x15182220 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x1000 0x400>;

			qcom,msm-bus,name = "apps_smmu";

			qcom,msm-bus,num-cases = <2>;

			qcom,msm-bus,active-only;

			qcom,msm-bus,num-paths = <1>;

			qcom,msm-bus,vectors-KBps =

				<MSM_BUS_MASTER_GEM_NOC_SNOC>,

				<MSM_BUS_SLAVE_IMEM_CFG>,

				<0 0>,

				<MSM_BUS_MASTER_GEM_NOC_SNOC>,

				<MSM_BUS_SLAVE_IMEM_CFG>,

				<0 1000>;

		};



		compute_dsp_0_tbu: compute_dsp_0_tbu@0x15199000 {
@@ -183,6 +239,17 @@ 
			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x1400 0x400>;

			/* No GDSC */

			qcom,msm-bus,name = "apps_smmu";

			qcom,msm-bus,num-cases = <2>;

			qcom,msm-bus,active-only;

			qcom,msm-bus,num-paths = <1>;

			qcom,msm-bus,vectors-KBps =

				<MSM_BUS_MASTER_NPU>,

				<MSM_BUS_SLAVE_CDSP_GEM_NOC>,

				<0 0>,

				<MSM_BUS_MASTER_NPU>,

				<MSM_BUS_SLAVE_CDSP_GEM_NOC>,

				<0 1000>;

		};

	};