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Commit 0f7513f7 authored by Deepak Kumar's avatar Deepak Kumar
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ARM: dts: msm: Correct GPU iommu protection range for SM8150 



GPU iommu registers on SM8150 starts at offset 0xA0000. Correct
the GPU iommu base offset to make sure iommu registers are
protected.

This also corrects GPU iommu context banks start offset and
removes property qcom,micro-mmu-control which is not needed
on SM8150.

Change-Id: I76c1e2c43a12132b4624ca1202d36d6423754ccf
Signed-off-by: default avatarDeepak Kumar <dkumar@codeaurora.org>
parent dfb894c5

arch/arm64/boot/dts/qcom/sm8150-gpu.dtsi

+2 −3
Original line number Diff line number Diff line
@@ -249,8 +249,7 @@ 


		reg = <0x02CA0000 0x10000>;

		/* CB5(ATOS) & CB5/6/7 are protected by HYP */

		qcom,protect = <0x40000 0xc000>;

		qcom,micro-mmu-control = <0x6000>;

		qcom,protect = <0xa0000 0xc000>;



		clocks =<&clock_gcc GCC_GPU_CFG_AHB_CLK>,

			<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,
@@ -266,7 +265,7 @@ 
			compatible = "qcom,smmu-kgsl-cb";

			label = "gfx3d_user";

			iommus = <&kgsl_smmu 0x0 0x401>;

			qcom,gpu-offset = <0x48000>;

			qcom,gpu-offset = <0xa8000>;

		};



		gfx3d_secure: gfx3d_secure {