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Commit 0efdf262 authored by Stephen Hemminger's avatar Stephen Hemminger Committed by Jeff Garzik
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[PATCH] sky2: sparse warnings 



Get rid of sparse warnings in sky2 driver because of mixed enum
usage.

Signed-off-by: default avatarStephen Hemminger <shemminger@osdl.org>
Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
parent 7f4b45c5

drivers/net/sky2.c

+4 −14
Original line number Original line Diff line number Diff line
@@ -521,7 +521,7 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port) 
		/* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */

		/* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */

		ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;

		ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;

		/* turn off the Rx LED (LED_RX) */

		/* turn off the Rx LED (LED_RX) */

		ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);

		ledover &= ~PHY_M_LED_MO_RX;

	}

	}





	if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {

	if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
@@ -544,7 +544,7 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port) 




		if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {

		if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {

			/* turn on 100 Mbps LED (LED_LINK100) */

			/* turn on 100 Mbps LED (LED_LINK100) */

			ledover |= PHY_M_LED_MO_100(MO_LED_ON);

			ledover |= PHY_M_LED_MO_100;

		}

		}





		if (ledover)

		if (ledover)
@@ -2931,17 +2931,7 @@ static void sky2_led(struct sky2_hw *hw, unsigned port, int on) 
	default:

	default:

		gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);

		gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);

		gm_phy_write(hw, port, PHY_MARV_LED_OVER, 

		gm_phy_write(hw, port, PHY_MARV_LED_OVER, 

			     on ? PHY_M_LED_MO_DUP(MO_LED_ON) |

			     on ? PHY_M_LED_ALL : 0);

			     PHY_M_LED_MO_10(MO_LED_ON) |

			     PHY_M_LED_MO_100(MO_LED_ON) |

			     PHY_M_LED_MO_1000(MO_LED_ON) |

			     PHY_M_LED_MO_RX(MO_LED_ON)

			     : PHY_M_LED_MO_DUP(MO_LED_OFF) |

			     PHY_M_LED_MO_10(MO_LED_OFF) |

			     PHY_M_LED_MO_100(MO_LED_OFF) |

			     PHY_M_LED_MO_1000(MO_LED_OFF) |

			     PHY_M_LED_MO_RX(MO_LED_OFF));



	}

	}

}

}

drivers/net/sky2.h

+25 −28
Original line number Original line Diff line number Diff line
@@ -608,7 +608,7 @@ enum { 
	PHY_ADDR_MARV	= 0,

	PHY_ADDR_MARV	= 0,

};

};





#define RB_ADDR(offs, queue) (B16_RAM_REGS + (queue) + (offs))

#define RB_ADDR(offs, queue) ((u16) B16_RAM_REGS + (queue) + (offs))









enum {

enum {
@@ -1061,7 +1061,7 @@ enum { 
	PHY_M_PC_EN_DET_PLUS	= 3<<8, /* Energy Detect Plus (Mode 2) */

	PHY_M_PC_EN_DET_PLUS	= 3<<8, /* Energy Detect Plus (Mode 2) */

};

};





#define PHY_M_PC_MDI_XMODE(x)	(((x)<<5) & PHY_M_PC_MDIX_MSK)

#define PHY_M_PC_MDI_XMODE(x)	(((u16)(x)<<5) & PHY_M_PC_MDIX_MSK)





enum {

enum {

	PHY_M_PC_MAN_MDI	= 0, /* 00 = Manual MDI configuration */

	PHY_M_PC_MAN_MDI	= 0, /* 00 = Manual MDI configuration */
@@ -1157,13 +1157,13 @@ enum { 
	PHY_M_EC_TX_TIM_CT  = 1<<1, /* RGMII Tx Timing Control */

	PHY_M_EC_TX_TIM_CT  = 1<<1, /* RGMII Tx Timing Control */

	PHY_M_EC_TRANS_DIS  = 1<<0, /* Transmitter Disable (88E1111 only) */};

	PHY_M_EC_TRANS_DIS  = 1<<0, /* Transmitter Disable (88E1111 only) */};





#define PHY_M_EC_M_DSC(x)	((x)<<10 & PHY_M_EC_M_DSC_MSK)

#define PHY_M_EC_M_DSC(x)	((u16)(x)<<10 & PHY_M_EC_M_DSC_MSK)

					/* 00=1x; 01=2x; 10=3x; 11=4x */

					/* 00=1x; 01=2x; 10=3x; 11=4x */

#define PHY_M_EC_S_DSC(x)	((x)<<8 & PHY_M_EC_S_DSC_MSK)

#define PHY_M_EC_S_DSC(x)	((u16)(x)<<8 & PHY_M_EC_S_DSC_MSK)

					/* 00=dis; 01=1x; 10=2x; 11=3x */

					/* 00=dis; 01=1x; 10=2x; 11=3x */

#define PHY_M_EC_DSC_2(x)	((x)<<9 & PHY_M_EC_M_DSC_MSK2)

#define PHY_M_EC_DSC_2(x)	((u16)(x)<<9 & PHY_M_EC_M_DSC_MSK2)

					/* 000=1x; 001=2x; 010=3x; 011=4x */

					/* 000=1x; 001=2x; 010=3x; 011=4x */

#define PHY_M_EC_MAC_S(x)	((x)<<4 & PHY_M_EC_MAC_S_MSK)

#define PHY_M_EC_MAC_S(x)	((u16)(x)<<4 & PHY_M_EC_MAC_S_MSK)

					/* 01X=0; 110=2.5; 111=25 (MHz) */

					/* 01X=0; 110=2.5; 111=25 (MHz) */





/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */

/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
@@ -1174,7 +1174,7 @@ enum { 
};

};

/* !!! Errata in spec. (1 = disable) */

/* !!! Errata in spec. (1 = disable) */





#define PHY_M_PC_DSC(x)			(((x)<<12) & PHY_M_PC_DSC_MSK)

#define PHY_M_PC_DSC(x)			(((u16)(x)<<12) & PHY_M_PC_DSC_MSK)

											/* 100=5x; 101=6x; 110=7x; 111=8x */

											/* 100=5x; 101=6x; 110=7x; 111=8x */

enum {

enum {

	MAC_TX_CLK_0_MHZ	= 2,

	MAC_TX_CLK_0_MHZ	= 2,
@@ -1204,7 +1204,7 @@ enum { 
	PHY_M_LEDC_TX_C_MSB	= 1<<0, /* Tx Control (MSB, 88E1111 only) */

	PHY_M_LEDC_TX_C_MSB	= 1<<0, /* Tx Control (MSB, 88E1111 only) */

};

};





#define PHY_M_LED_PULS_DUR(x)	(((x)<<12) & PHY_M_LEDC_PULS_MSK)

#define PHY_M_LED_PULS_DUR(x)	(((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK)





/*****  PHY_MARV_PHY_STAT (page 3)16 bit r/w	Polarity Control Reg. *****/

/*****  PHY_MARV_PHY_STAT (page 3)16 bit r/w	Polarity Control Reg. *****/

enum {

enum {
@@ -1234,7 +1234,7 @@ enum { 
	PULS_1300MS	= 7,/* 1.3 s to 2.7 s */

	PULS_1300MS	= 7,/* 1.3 s to 2.7 s */

};

};





#define PHY_M_LED_BLINK_RT(x)	(((x)<<8) & PHY_M_LEDC_BL_R_MSK)

#define PHY_M_LED_BLINK_RT(x)	(((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK)





enum {

enum {

	BLINK_42MS	= 0,/* 42 ms */

	BLINK_42MS	= 0,/* 42 ms */
@@ -1244,21 +1244,18 @@ enum { 
	BLINK_670MS	= 4,/* 670 ms */

	BLINK_670MS	= 4,/* 670 ms */

};

};





/*****  PHY_MARV_LED_OVER	16 bit r/w	Manual LED Override Reg *****/

/**** PHY_MARV_LED_OVER    16 bit r/w LED control */

#define PHY_M_LED_MO_SGMII(x)	((x)<<14) /* Bit 15..14:  SGMII AN Timer */

										/* Bit 13..12:	reserved */

#define PHY_M_LED_MO_DUP(x)	((x)<<10) /* Bit 11..10:  Duplex */

#define PHY_M_LED_MO_10(x)	((x)<<8) /* Bit  9.. 8:  Link 10 */

#define PHY_M_LED_MO_100(x)	((x)<<6) /* Bit  7.. 6:  Link 100 */

#define PHY_M_LED_MO_1000(x)	((x)<<4) /* Bit  5.. 4:  Link 1000 */

#define PHY_M_LED_MO_RX(x)	((x)<<2) /* Bit  3.. 2:  Rx */

#define PHY_M_LED_MO_TX(x)	((x)<<0) /* Bit  1.. 0:  Tx */



enum {

enum {

	MO_LED_NORM	= 0,

	PHY_M_LED_MO_DUP  = 3<<10,/* Bit 11..10:  Duplex */

	MO_LED_BLINK	= 1,

	PHY_M_LED_MO_10	  = 3<<8, /* Bit  9.. 8:  Link 10 */

	MO_LED_OFF	= 2,

	PHY_M_LED_MO_100  = 3<<6, /* Bit  7.. 6:  Link 100 */

	MO_LED_ON	= 3,

	PHY_M_LED_MO_1000 = 3<<4, /* Bit  5.. 4:  Link 1000 */

	PHY_M_LED_MO_RX	  = 3<<2, /* Bit  3.. 2:  Rx */

	PHY_M_LED_MO_TX	  = 3<<0, /* Bit  1.. 0:  Tx */



	PHY_M_LED_ALL	  = PHY_M_LED_MO_DUP | PHY_M_LED_MO_10 

			    | PHY_M_LED_MO_100 | PHY_M_LED_MO_1000

			    | PHY_M_LED_MO_RX,

};

};





/*****  PHY_MARV_EXT_CTRL_2	16 bit r/w	Ext. PHY Specific Ctrl 2 *****/

/*****  PHY_MARV_EXT_CTRL_2	16 bit r/w	Ext. PHY Specific Ctrl 2 *****/
@@ -1295,9 +1292,9 @@ enum { 
	PHY_M_FELP_LED0_MSK = 0xf, /* Bit  3.. 0: LED0 Mask (SPEED) */

	PHY_M_FELP_LED0_MSK = 0xf, /* Bit  3.. 0: LED0 Mask (SPEED) */

};

};





#define PHY_M_FELP_LED2_CTRL(x)	(((x)<<8) & PHY_M_FELP_LED2_MSK)

#define PHY_M_FELP_LED2_CTRL(x)	(((u16)(x)<<8) & PHY_M_FELP_LED2_MSK)

#define PHY_M_FELP_LED1_CTRL(x)	(((x)<<4) & PHY_M_FELP_LED1_MSK)

#define PHY_M_FELP_LED1_CTRL(x)	(((u16)(x)<<4) & PHY_M_FELP_LED1_MSK)

#define PHY_M_FELP_LED0_CTRL(x)	(((x)<<0) & PHY_M_FELP_LED0_MSK)

#define PHY_M_FELP_LED0_CTRL(x)	(((u16)(x)<<0) & PHY_M_FELP_LED0_MSK)





enum {

enum {

	LED_PAR_CTRL_COLX	= 0x00,

	LED_PAR_CTRL_COLX	= 0x00,
@@ -1553,8 +1550,8 @@ enum { 
	GM_SMI_CT_BUSY		= 1<<3,	/* Bit  3:	Busy (Operation in progress) */

	GM_SMI_CT_BUSY		= 1<<3,	/* Bit  3:	Busy (Operation in progress) */

};

};





#define GM_SMI_CT_PHY_AD(x)	(((x)<<11) & GM_SMI_CT_PHY_A_MSK)

#define GM_SMI_CT_PHY_AD(x)	(((u16)(x)<<11) & GM_SMI_CT_PHY_A_MSK)

#define GM_SMI_CT_REG_AD(x)	(((x)<<6) & GM_SMI_CT_REG_A_MSK)

#define GM_SMI_CT_REG_AD(x)	(((u16)(x)<<6) & GM_SMI_CT_REG_A_MSK)





/*	GM_PHY_ADDR				16 bit r/w	GPHY Address Register */

/*	GM_PHY_ADDR				16 bit r/w	GPHY Address Register */

enum {

enum {