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Commit 0e6615a0 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "msm: msm_bus: Add node clock support for each bus node"

parents 7a3afdb4 07f69910

arch/arm64/boot/dts/qcom/trinket-bus.dtsi

0 → 100644
+1099 −0

File added.

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arch/arm64/boot/dts/qcom/trinket.dtsi

+1 −0
Original line number Original line Diff line number Diff line
@@ -2179,6 +2179,7 @@ 
#include "trinket-vidc.dtsi"

#include "trinket-vidc.dtsi"

#include "trinket-pm.dtsi"

#include "trinket-pm.dtsi"

#include "trinket-gpu.dtsi"

#include "trinket-gpu.dtsi"

#include "trinket-bus.dtsi"





&pm6125_vadc {

&pm6125_vadc {

	pinctrl-names = "default";

	pinctrl-names = "default";

drivers/soc/qcom/msm_bus/msm_bus_of_adhoc.c

+10 −1
Original line number Original line Diff line number Diff line 
/* Copyright (c) 2014-2016, 2018, The Linux Foundation. All rights reserved.

/* Copyright (c) 2014-2016, 2018-2019, The Linux Foundation. All rights reserved.

 *

 *

 * This program is free software; you can redistribute it and/or modify

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * it under the terms of the GNU General Public License version 2 and
@@ -656,6 +656,15 @@ static int get_bus_node_device_data( 
			of_node_put(qos_clk_node);

			of_node_put(qos_clk_node);

		}

		}





		node_device->clk[ACTIVE_CTX].clk = of_clk_get_by_name(dev_node,

							"node_a_clk");



		if (IS_ERR_OR_NULL(node_device->clk[ACTIVE_CTX].clk))

			dev_dbg(&pdev->dev,

				 "%s:Failed to get bus clk for bus%d ctx%d",

				__func__, node_device->node_info->id,

								ACTIVE_CTX);



		node_device->clk[DUAL_CTX].clk = of_clk_get_by_name(dev_node,

		node_device->clk[DUAL_CTX].clk = of_clk_get_by_name(dev_node,

							"node_clk");

							"node_clk");

include/dt-bindings/msm/msm-bus-ids.h

+47 −0
Original line number Original line Diff line number Diff line
@@ -46,6 +46,7 @@ 
#define	MSM_BUS_FAB_CAMNOC_VIRT 6154

#define	MSM_BUS_FAB_CAMNOC_VIRT 6154

#define	MSM_BUS_FAB_COMP_NOC 6155

#define	MSM_BUS_FAB_COMP_NOC 6155

#define	MSM_BUS_FAB_GEM_NOC 6156

#define	MSM_BUS_FAB_GEM_NOC 6156

#define	MSM_BUS_FAB_QUP_VIRT 6157





#define	MSM_BUS_FAB_MC_VIRT_DISPLAY 26000

#define	MSM_BUS_FAB_MC_VIRT_DISPLAY 26000

#define	MSM_BUS_FAB_MEM_NOC_DISPLAY 26001

#define	MSM_BUS_FAB_MEM_NOC_DISPLAY 26001
@@ -299,6 +300,11 @@ 
#define	MSM_BUS_MASTER_MEM_NOC_PCIE_SNOC 177

#define	MSM_BUS_MASTER_MEM_NOC_PCIE_SNOC 177

#define	MSM_BUS_MASTER_CAMNOC_RT_UNCOMP 178

#define	MSM_BUS_MASTER_CAMNOC_RT_UNCOMP 178

#define	MSM_BUS_MASTER_CAMNOC_NRT_UNCOMP 179

#define	MSM_BUS_MASTER_CAMNOC_NRT_UNCOMP 179

#define	MSM_BUS_MASTER_SNOC_BIMC_RT 180

#define	MSM_BUS_MASTER_SNOC_BIMC_NRT 181

#define	MSM_BUS_MASTER_GPU_CDSP_PROC 182

#define	MSM_BUS_MASTER_QUP_CORE_0 183

#define	MSM_BUS_MASTER_QUP_CORE_1 184





#define	MSM_BUS_MASTER_LLCC_DISPLAY 20000

#define	MSM_BUS_MASTER_LLCC_DISPLAY 20000

#define	MSM_BUS_MASTER_MNOC_HF_MEM_NOC_DISPLAY 20001

#define	MSM_BUS_MASTER_MNOC_HF_MEM_NOC_DISPLAY 20001
@@ -682,6 +688,14 @@ 
#define	MSM_BUS_SLAVE_ANOC_IPA 812

#define	MSM_BUS_SLAVE_ANOC_IPA 812

#define	MSM_BUS_SLAVE_ECC_CFG 813

#define	MSM_BUS_SLAVE_ECC_CFG 813

#define	MSM_BUS_SLAVE_SPMI_VGI_COEX 814

#define	MSM_BUS_SLAVE_SPMI_VGI_COEX 814

#define	MSM_BUS_SLAVE_GPU_CFG 815

#define	MSM_BUS_SLAVE_QUP_CORE_0 816

#define	MSM_BUS_SLAVE_QUP_CORE_1 817

#define	MSM_BUS_SLAVE_SNOC_BIMC_NRT 818

#define	MSM_BUS_SLAVE_SNOC_BIMC_RT 819

#define	MSM_BUS_SLAVE_GPU_CDSP_BIMC 820

#define	MSM_BUS_SLAVE_QM_MPU_CFG 821

#define MSM_BUS_SLAVE_CDSP_THROTTLE_CFG 822





#define	MSM_BUS_SLAVE_EBI_CH0_DISPLAY 20512

#define	MSM_BUS_SLAVE_EBI_CH0_DISPLAY 20512

#define	MSM_BUS_SLAVE_LLCC_DISPLAY 20513

#define	MSM_BUS_SLAVE_LLCC_DISPLAY 20513
@@ -744,6 +758,7 @@ 
#define	ICBID_MASTER_BLSP_2 39

#define	ICBID_MASTER_BLSP_2 39

#define	ICBID_MASTER_USB_HSIC 40

#define	ICBID_MASTER_USB_HSIC 40

#define	ICBID_MASTER_BLSP_1 41

#define	ICBID_MASTER_BLSP_1 41

#define	ICBID_MASTER_QUP_1 ICBID_MASTER_BLSP_1

#define	ICBID_MASTER_USB_HS 42

#define	ICBID_MASTER_USB_HS 42

#define	ICBID_MASTER_USB_HS1 ICBID_MASTER_USB_HS

#define	ICBID_MASTER_USB_HS1 ICBID_MASTER_USB_HS

#define	ICBID_MASTER_PNOC_CFG 43

#define	ICBID_MASTER_PNOC_CFG 43
@@ -869,6 +884,16 @@ 
#define	ICBID_MASTER_LPASS_LPAIF 159

#define	ICBID_MASTER_LPASS_LPAIF 159

#define	ICBID_MASTER_LPASS_LEC 160

#define	ICBID_MASTER_LPASS_LEC 160

#define	ICBID_MASTER_LPASS_ANOC_BIMC 161

#define	ICBID_MASTER_LPASS_ANOC_BIMC 161

#define	ICBID_MASTER_MCDMA_NAV_CE 162

#define	ICBID_MASTER_SNOC_BIMC_RT 163

#define	ICBID_MASTER_SNOC_BIMC_NRT 164

#define	ICBID_MASTER_GPU_CDSP_PROC 165

#define	ICBID_MASTER_QUP_0 166

#define	ICBID_MASTER_UFS_MEM 167

#define	ICBID_MASTER_VIDEO_PROC 168

#define	ICBID_MASTER_LPASS_DMA 169

#define	ICBID_MASTER_QUP_CORE_0 170

#define	ICBID_MASTER_QUP_CORE_1 171





#define	ICBID_SLAVE_EBI1 0

#define	ICBID_SLAVE_EBI1 0

#define	ICBID_SLAVE_APPSS_L2 1

#define	ICBID_SLAVE_APPSS_L2 1
@@ -917,6 +942,7 @@ 
#define	ICBID_SLAVE_BLSP_2 37

#define	ICBID_SLAVE_BLSP_2 37

#define	ICBID_SLAVE_USB_HSIC 38

#define	ICBID_SLAVE_USB_HSIC 38

#define	ICBID_SLAVE_BLSP_1 39

#define	ICBID_SLAVE_BLSP_1 39

#define	ICBID_SLAVE_QUP_1 ICBID_SLAVE_BLSP_1

#define	ICBID_SLAVE_USB_HS 40

#define	ICBID_SLAVE_USB_HS 40

#define	ICBID_SLAVE_USB_HS1 ICBID_SLAVE_USB_HS

#define	ICBID_SLAVE_USB_HS1 ICBID_SLAVE_USB_HS

#define	ICBID_SLAVE_PDM 41

#define	ICBID_SLAVE_PDM 41
@@ -1129,4 +1155,25 @@ 
#define	ICBID_SLAVE_PCNOC_S_10 245

#define	ICBID_SLAVE_PCNOC_S_10 245

#define	ICBID_SLAVE_PCNOC_S_11 246

#define	ICBID_SLAVE_PCNOC_S_11 246

#define	ICBID_SLAVE_LPASS_ANOC_BIMC 247

#define	ICBID_SLAVE_LPASS_ANOC_BIMC 247

#define	ICBID_SLAVE_SNOC_BIMC_NRT 259

#define	ICBID_SLAVE_SNOC_BIMC_RT 260

#define	ICBID_SLAVE_QUP_0 261

#define	ICBID_SLAVE_UFS_MEM_CFG 262

#define	ICBID_SLAVE_VSENSE_CTRL_CFG 263

#define	ICBID_SLAVE_QUP_CORE_0 264

#define	ICBID_SLAVE_QUP_CORE_1 265

#define	ICBID_SLAVE_GPU_CDSP_BIMC 266

#define	ICBID_SLAVE_AHB2PHY_CSI 267

#define	ICBID_SLAVE_AHB2PHY_USB 268

#define	CBID_SLAVE_AHB2PHY_VREF 269

#define	ICBID_SLAVE_APSS_THROTTLE_CFG 270

#define	ICBID_SLAVE_CAMERA_NRT_THROTTLE_CFG 271

#define	ICBID_SLAVE_CDSP_THROTTLE_CFG 272

#define	ICBID_SLAVE_DDR_PHY_CFG 273

#define	ICBID_SLAVE_DDR_SS_CFG 274

#define	ICBID_SLAVE_GPU_CFG 275

#define	ICBID_SLAVE_GPU_THROTTLE_CFG 276

#define	ICBID_SLAVE_MAPSS 277

#define	ICBID_SLAVE_MDSP_MPU_CFG 278

#define	ICBID_SLAVE_CAMERA_RT_THROTTLE_CFG 279

#endif
 
#endif