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Commit 0ddaa974 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-radeon-sun-hainan' of git://people.freedesktop.org/~airlied/linux 

Pull radeon sun/hainan support from  Dave Airlie:
 "Since I know its outside the merge window, but since this is new hw I
  thought I'd try and provoke the new hw exception, it just fills in the
  blanks in the driver for the new AMD sun and hainan chipsets."

* 'drm-radeon-sun-hainan' of git://people.freedesktop.org/~airlied/linux:
  drm/radeon: add Hainan pci ids
  drm/radeon: add golden register settings for Hainan (v2)
  drm/radeon: sun/hainan chips do not have UVD (v2)
  drm/radeon: track which asics have UVD
  drm/radeon: radeon-asic updates for Hainan
  drm/radeon: fill in ucode loading support for Hainan
  drm/radeon: don't touch DCE or VGA regs on Hainan (v3)
  drm/radeon: fill in GPU init for Hainan (v2)
  drm/radeon: add chip family for Hainan
parents 007b703b cc3e06a5

drivers/gpu/drm/radeon/evergreen.c

+17 −10
Original line number Diff line number Diff line
@@ -2343,11 +2343,13 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav 
	u32 crtc_enabled, tmp, frame_count, blackout;

	int i, j;



	if (!ASIC_IS_NODCE(rdev)) {

		save->vga_render_control = RREG32(VGA_RENDER_CONTROL);

		save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);



		/* disable VGA render */

		WREG32(VGA_RENDER_CONTROL, 0);

	}

	/* blank the display controllers */

	for (i = 0; i < rdev->num_crtc; i++) {

		crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
@@ -2438,8 +2440,11 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s 
		WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],

		       (u32)rdev->mc.vram_start);

	}



	if (!ASIC_IS_NODCE(rdev)) {

		WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));

		WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);

	}



	/* unlock regs and wait for update */

	for (i = 0; i < rdev->num_crtc; i++) {
@@ -2499,11 +2504,13 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s 
			}

		}

	}

	if (!ASIC_IS_NODCE(rdev)) {

		/* Unlock vga access */

		WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);

		mdelay(1);

		WREG32(VGA_RENDER_CONTROL, save->vga_render_control);

	}

}



void evergreen_mc_program(struct radeon_device *rdev)

{

drivers/gpu/drm/radeon/radeon.h

+2 −0
Original line number Diff line number Diff line
@@ -1694,6 +1694,7 @@ struct radeon_device { 
	int num_crtc; /* number of crtcs */

	struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */

	bool audio_enabled;

	bool has_uvd;

	struct r600_audio audio_status; /* audio stuff */

	struct notifier_block acpi_nb;

	/* only one userspace can use Hyperz features or CMASK at a time */
@@ -1838,6 +1839,7 @@ void r100_pll_errata_after_index(struct radeon_device *rdev); 
#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \

			     (rdev->flags & RADEON_IS_IGP))

#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))

#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))



/*

 * BIOS helpers.

drivers/gpu/drm/radeon/radeon_asic.c

+21 −1
Original line number Diff line number Diff line
@@ -1935,6 +1935,8 @@ int radeon_asic_init(struct radeon_device *rdev) 
	else

		rdev->num_crtc = 2;



	rdev->has_uvd = false;



	switch (rdev->family) {

	case CHIP_R100:

	case CHIP_RV100:
@@ -1999,16 +2001,22 @@ int radeon_asic_init(struct radeon_device *rdev) 
	case CHIP_RV635:

	case CHIP_RV670:

		rdev->asic = &r600_asic;

		if (rdev->family == CHIP_R600)

			rdev->has_uvd = false;

		else

			rdev->has_uvd = true;

		break;

	case CHIP_RS780:

	case CHIP_RS880:

		rdev->asic = &rs780_asic;

		rdev->has_uvd = true;

		break;

	case CHIP_RV770:

	case CHIP_RV730:

	case CHIP_RV710:

	case CHIP_RV740:

		rdev->asic = &rv770_asic;

		rdev->has_uvd = true;

		break;

	case CHIP_CEDAR:

	case CHIP_REDWOOD:
@@ -2021,11 +2029,13 @@ int radeon_asic_init(struct radeon_device *rdev) 
		else

			rdev->num_crtc = 6;

		rdev->asic = &evergreen_asic;

		rdev->has_uvd = true;

		break;

	case CHIP_PALM:

	case CHIP_SUMO:

	case CHIP_SUMO2:

		rdev->asic = &sumo_asic;

		rdev->has_uvd = true;

		break;

	case CHIP_BARTS:

	case CHIP_TURKS:
@@ -2036,27 +2046,37 @@ int radeon_asic_init(struct radeon_device *rdev) 
		else

			rdev->num_crtc = 6;

		rdev->asic = &btc_asic;

		rdev->has_uvd = true;

		break;

	case CHIP_CAYMAN:

		rdev->asic = &cayman_asic;

		/* set num crtcs */

		rdev->num_crtc = 6;

		rdev->has_uvd = true;

		break;

	case CHIP_ARUBA:

		rdev->asic = &trinity_asic;

		/* set num crtcs */

		rdev->num_crtc = 4;

		rdev->has_uvd = true;

		break;

	case CHIP_TAHITI:

	case CHIP_PITCAIRN:

	case CHIP_VERDE:

	case CHIP_OLAND:

	case CHIP_HAINAN:

		rdev->asic = &si_asic;

		/* set num crtcs */

		if (rdev->family == CHIP_OLAND)

		if (rdev->family == CHIP_HAINAN)

			rdev->num_crtc = 0;

		else if (rdev->family == CHIP_OLAND)

			rdev->num_crtc = 2;

		else

			rdev->num_crtc = 6;

		if (rdev->family == CHIP_HAINAN)

			rdev->has_uvd = false;

		else

			rdev->has_uvd = true;

		break;

	default:

		/* FIXME: not supported yet */

drivers/gpu/drm/radeon/radeon_bios.c

+16 −12
Original line number Diff line number Diff line
@@ -244,6 +244,7 @@ static bool ni_read_disabled_bios(struct radeon_device *rdev) 


	/* enable the rom */

	WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));

	if (!ASIC_IS_NODCE(rdev)) {

		/* Disable VGA mode */

		WREG32(AVIVO_D1VGA_CONTROL,

		       (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
@@ -253,15 +254,18 @@ static bool ni_read_disabled_bios(struct radeon_device *rdev) 
					  AVIVO_DVGA_CONTROL_TIMING_SELECT)));

		WREG32(AVIVO_VGA_RENDER_CONTROL,

		       (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));

	}

	WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);



	r = radeon_read_bios(rdev);



	/* restore regs */

	WREG32(R600_BUS_CNTL, bus_cntl);

	if (!ASIC_IS_NODCE(rdev)) {

		WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);

		WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);

		WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);

	}

	WREG32(R600_ROM_CNTL, rom_cntl);

	return r;

}

drivers/gpu/drm/radeon/radeon_device.c

+1 −0
Original line number Diff line number Diff line
@@ -94,6 +94,7 @@ static const char radeon_family_name[][16] = { 
	"PITCAIRN",

	"VERDE",

	"OLAND",

	"HAINAN",

	"LAST",

};