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Commit 0dd87d20 authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter
Browse files

drm/i915: explicitly disable the DIPs we're not using 



From this point on, the 'set_infoframe' functions always set the DIP
registers to a known state, so anything done will always be undone at
the modeset.

Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 5cde2a62

drivers/gpu/drm/i915/i915_reg.h

+6 −0
Original line number Diff line number Diff line
@@ -1717,8 +1717,10 @@ 
#define   VIDEO_DIP_PORT_C		(2 << 29)

#define   VIDEO_DIP_PORT_D		(3 << 29)

#define   VIDEO_DIP_PORT_MASK		(3 << 29)

#define   VIDEO_DIP_ENABLE_GCP		(1 << 25)

#define   VIDEO_DIP_ENABLE_AVI		(1 << 21)

#define   VIDEO_DIP_ENABLE_VENDOR	(2 << 21)

#define   VIDEO_DIP_ENABLE_GAMUT	(4 << 21)

#define   VIDEO_DIP_ENABLE_SPD		(8 << 21)

#define   VIDEO_DIP_SELECT_AVI		(0 << 19)

#define   VIDEO_DIP_SELECT_VENDOR	(1 << 19)
@@ -1729,7 +1731,11 @@ 
#define   VIDEO_DIP_FREQ_2VSYNC		(2 << 16)

#define   VIDEO_DIP_FREQ_MASK		(3 << 16)

/* HSW and later: */

#define   VIDEO_DIP_ENABLE_VSC_HSW	(1 << 20)

#define   VIDEO_DIP_ENABLE_GCP_HSW	(1 << 16)

#define   VIDEO_DIP_ENABLE_AVI_HSW	(1 << 12)

#define   VIDEO_DIP_ENABLE_VS_HSW	(1 << 8)

#define   VIDEO_DIP_ENABLE_GMP_HSW	(1 << 4)

#define   VIDEO_DIP_ENABLE_SPD_HSW	(1 << 0)



/* Panel power sequencing */

drivers/gpu/drm/i915/intel_hdmi.c

+13 −0
Original line number Diff line number Diff line
@@ -350,6 +350,7 @@ static void g4x_set_infoframes(struct drm_encoder *encoder, 
	}



	val |= VIDEO_DIP_ENABLE;

	val &= ~VIDEO_DIP_ENABLE_VENDOR;



	I915_WRITE(reg, val);
@@ -393,6 +394,8 @@ static void ibx_set_infoframes(struct drm_encoder *encoder, 
	}



	val |= VIDEO_DIP_ENABLE;

	val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |

		 VIDEO_DIP_ENABLE_GCP);



	I915_WRITE(reg, val);
@@ -422,6 +425,8 @@ static void cpt_set_infoframes(struct drm_encoder *encoder, 


	/* Set both together, unset both together: see the spec. */

	val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;

	val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |

		 VIDEO_DIP_ENABLE_GCP);



	I915_WRITE(reg, val);
@@ -450,6 +455,8 @@ static void vlv_set_infoframes(struct drm_encoder *encoder, 
	}



	val |= VIDEO_DIP_ENABLE;

	val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |

		 VIDEO_DIP_ENABLE_GCP);



	I915_WRITE(reg, val);
@@ -464,12 +471,18 @@ static void hsw_set_infoframes(struct drm_encoder *encoder, 
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);

	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);

	u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);

	u32 val = I915_READ(reg);



	if (!intel_hdmi->has_hdmi_sink) {

		I915_WRITE(reg, 0);

		return;

	}



	val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |

		 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);



	I915_WRITE(reg, val);



	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);

	intel_hdmi_set_spd_infoframe(encoder);

}