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Commit 0ce3faf0 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "power: qpnp-fg-gen3: Reorganize the FG driver" into msm-4.14

parents ec69d9e6 f20ed3dd

drivers/power/supply/qcom/fg-core.h

+96 −113
Original line number Diff line number Diff line
@@ -31,9 +31,9 @@ 
#include <linux/uaccess.h>

#include <linux/pmic-voter.h>



#define fg_dbg(chip, reason, fmt, ...)			\

#define fg_dbg(fg, reason, fmt, ...)			\

	do {							\

		if (*chip->debug_mask & (reason))		\

		if (*fg->debug_mask & (reason))		\

			pr_info(fmt, ##__VA_ARGS__);	\

		else						\

			pr_debug(fmt, ##__VA_ARGS__);	\
@@ -45,6 +45,19 @@ 
		|| ((left) <= (right) && (left) <= (value) \

			&& (value) <= (right)))



#define PARAM(_id, _addr_word, _addr_byte, _len, _num, _den, _offset,	\

	      _enc, _dec)						\

	[FG_SRAM_##_id] = {						\

		.addr_word	= _addr_word,				\

		.addr_byte	= _addr_byte,				\

		.len		= _len,					\

		.numrtr		= _num,					\

		.denmtr		= _den,					\

		.offset		= _offset,				\

		.encode		= _enc,					\

		.decode		= _dec,					\

	}								\



/* Awake votable reasons */

#define SRAM_READ		"fg_sram_read"

#define SRAM_WRITE		"fg_sram_write"
@@ -59,32 +72,17 @@ 


#define ESR_FCC_VOTER		"fg_esr_fcc"



#define DEBUG_PRINT_BUFFER_SIZE		64

/* 3 byte address + 1 space character */

#define ADDR_LEN			4

/* Format is 'XX ' */

#define CHARS_PER_ITEM			3

/* 4 data items per line */

#define ITEMS_PER_LINE			4

#define MAX_LINE_LENGTH			(ADDR_LEN + (ITEMS_PER_LINE *	\

					CHARS_PER_ITEM) + 1)		\



#define NUM_PARTITIONS			3

#define FG_SRAM_ADDRESS_MAX		255

#define FG_SRAM_LEN			504

#define PROFILE_LEN			224

#define PROFILE_COMP_LEN		148

#define BUCKET_COUNT			8

#define BUCKET_SOC_PCT			(256 / BUCKET_COUNT)



#define KI_COEFF_MAX			62200

#define KI_COEFF_SOC_LEVELS		3



#define SLOPE_LIMIT_COEFF_MAX		31

#define MAX_CC_STEPS			20



#define BATT_THERM_NUM_COEFFS		3

#define FULL_CAPACITY			100

#define FULL_SOC_RAW			255



#define MAX_CC_STEPS			20

#define DEBUG_BATT_SOC			67

#define BATT_MISS_SOC			50

#define EMPTY_SOC			0



enum prof_load_status {

	PROFILE_MISSING,
@@ -124,6 +122,7 @@ enum jeita_levels { 


/* FG irqs */

enum fg_irq_index {

	/* FG_BATT_SOC */

	MSOC_FULL_IRQ = 0,

	MSOC_HIGH_IRQ,

	MSOC_EMPTY_IRQ,
@@ -132,15 +131,17 @@ enum fg_irq_index { 
	BSOC_DELTA_IRQ,

	SOC_READY_IRQ,

	SOC_UPDATE_IRQ,

	/* FG_BATT_INFO */

	BATT_TEMP_DELTA_IRQ,

	BATT_MISSING_IRQ,

	ESR_DELTA_IRQ,

	VBATT_LOW_IRQ,

	VBATT_PRED_DELTA_IRQ,

	/* FG_MEM_IF */

	DMA_GRANT_IRQ,

	MEM_XCP_IRQ,

	IMA_RDY_IRQ,

	FG_IRQ_MAX,

	FG_GEN3_IRQ_MAX,

};



/*
@@ -228,6 +229,10 @@ enum fg_alg_flag_id { 
	ALG_FLAG_MAX,

};



enum fg_version {

	GEN3_FG = 1,

};



struct fg_alg_flag {

	char	*name;

	u8	bit;
@@ -258,55 +263,6 @@ enum ttf_mode { 
	TTF_MODE_QNOVO,

};



/* DT parameters for FG device */

struct fg_dt_props {

	bool	force_load_profile;

	bool	hold_soc_while_full;

	bool	linearize_soc;

	bool	auto_recharge_soc;

	int	cutoff_volt_mv;

	int	empty_volt_mv;

	int	vbatt_low_thr_mv;

	int	chg_term_curr_ma;

	int	chg_term_base_curr_ma;

	int	sys_term_curr_ma;

	int	cutoff_curr_ma;

	int	delta_soc_thr;

	int	recharge_soc_thr;

	int	recharge_volt_thr_mv;

	int	rsense_sel;

	int	esr_timer_charging[NUM_ESR_TIMERS];

	int	esr_timer_awake[NUM_ESR_TIMERS];

	int	esr_timer_asleep[NUM_ESR_TIMERS];

	int	rconn_mohms;

	int	esr_clamp_mohms;

	int	cl_start_soc;

	int	cl_max_temp;

	int	cl_min_temp;

	int	cl_max_cap_inc;

	int	cl_max_cap_dec;

	int	cl_max_cap_limit;

	int	cl_min_cap_limit;

	int	jeita_hyst_temp;

	int	batt_temp_delta;

	int	esr_flt_switch_temp;

	int	esr_tight_flt_upct;

	int	esr_broad_flt_upct;

	int	esr_tight_lt_flt_upct;

	int	esr_broad_lt_flt_upct;

	int	slope_limit_temp;

	int	esr_pulse_thresh_ma;

	int	esr_meas_curr_ma;

	int	bmd_en_delay_ms;

	int	ki_coeff_full_soc_dischg;

	int	jeita_thresholds[NUM_JEITA_LEVELS];

	int	ki_coeff_soc[KI_COEFF_SOC_LEVELS];

	int	ki_coeff_med_dischg[KI_COEFF_SOC_LEVELS];

	int	ki_coeff_hi_dischg[KI_COEFF_SOC_LEVELS];

	int	slope_limit_coeffs[SLOPE_LIMIT_NUM_COEFFS];

	u8	batt_therm_coeffs[BATT_THERM_NUM_COEFFS];

};



/* parameters from battery profile */

struct fg_batt_props {

	const char	*batt_type_str;
@@ -397,7 +353,14 @@ static const struct fg_pt fg_tsmc_osc_table[] = { 
	{  90,		444992 },

};



struct fg_chip {

struct fg_memif {

	struct fg_dma_address	*addr_map;

	int			num_partitions;

	u16			address_max;

	u8			num_bytes_per_word;

};



struct fg_dev {

	struct device		*dev;

	struct pmic_revid_data	*pmic_rev_id;

	struct regmap		*regmap;
@@ -408,24 +371,16 @@ struct fg_chip { 
	struct power_supply	*dc_psy;

	struct power_supply	*parallel_psy;

	struct power_supply	*pc_port_psy;

	struct iio_channel	*batt_id_chan;

	struct iio_channel	*die_temp_chan;

	struct fg_irq_info	*irqs;

	struct votable		*awake_votable;

	struct votable		*delta_bsoc_irq_en_votable;

	struct votable		*batt_miss_irq_en_votable;

	struct votable		*pl_disable_votable;

	struct fg_sram_param	*sp;

	struct fg_dma_address	*addr_map;

	struct fg_memif		sram;

	struct fg_alg_flag	*alg_flags;

	int			*debug_mask;

	char			batt_profile[PROFILE_LEN];

	struct fg_dt_props	dt;

	struct fg_batt_props	bp;

	struct fg_cyc_ctr_data	cyc_ctr;

	struct notifier_block	nb;

	struct fg_cap_learning  cl;

	struct ttf		ttf;

	struct mutex		bus_lock;

	struct mutex		sram_rw_lock;

	struct mutex		charge_full_lock;
@@ -436,7 +391,6 @@ struct fg_chip { 
	u32			rradc_base;

	u32			wa_flags;

	int			batt_id_ohms;

	int			ki_coeff_full_soc;

	int			charge_status;

	int			prev_charge_status;

	int			charge_done;
@@ -449,8 +403,6 @@ struct fg_chip { 
	int			delta_soc;

	int			last_msoc;

	int			last_recharge_volt_mv;

	int			esr_timer_charging_default[NUM_ESR_TIMERS];

	enum slope_limit_status	slope_limit_sts;

	bool			profile_available;

	bool			profile_loaded;

	enum prof_load_status	profile_load_status;
@@ -458,21 +410,16 @@ struct fg_chip { 
	bool			fg_restarting;

	bool			charge_full;

	bool			recharge_soc_adjusted;

	bool			ki_coeff_dischg_en;

	bool			esr_fcc_ctrl_en;

	bool			soc_reporting_ready;

	bool			esr_flt_cold_temp_en;

	bool			slope_limit_en;

	bool			use_ima_single_mode;

	bool			use_dma;

	bool			qnovo_enable;

	enum fg_version		version;

	struct completion	soc_update;

	struct completion	soc_ready;

	struct delayed_work	profile_load_work;

	struct work_struct	status_change_work;

	struct delayed_work	ttf_work;

	struct delayed_work	sram_dump_work;

	struct delayed_work	pl_enable_work;

};



/* Debugfs data structures are below */
@@ -487,7 +434,7 @@ struct fg_log_buffer { 


/* transaction parameters */

struct fg_trans {

	struct fg_chip		*chip;

	struct fg_dev		*fg;

	struct mutex		fg_dfs_lock; /* Prevent thread concurrency */

	struct fg_log_buffer	*log;

	u32			cnt;
@@ -498,41 +445,77 @@ struct fg_trans { 


struct fg_dbgfs {

	struct debugfs_blob_wrapper	help_msg;

	struct fg_chip			*chip;

	struct fg_dev			*fg;

	struct dentry			*root;

	u32				cnt;

	u32				addr;

};



extern int fg_sram_write(struct fg_chip *chip, u16 address, u8 offset,

extern int fg_decode_voltage_15b(struct fg_sram_param *sp,

	enum fg_sram_param_id id, int val);

extern int fg_decode_cc_soc(struct fg_sram_param *sp,

	enum fg_sram_param_id id, int value);

extern int fg_decode_value_16b(struct fg_sram_param *sp,

	enum fg_sram_param_id id, int val);

extern int fg_decode_default(struct fg_sram_param *sp,

	enum fg_sram_param_id id, int val);

extern int fg_decode(struct fg_sram_param *sp,

	enum fg_sram_param_id id, int val);

extern void fg_encode_voltage(struct fg_sram_param *sp,

	enum fg_sram_param_id id, int val_mv, u8 *buf);

extern void fg_encode_current(struct fg_sram_param *sp,

	enum fg_sram_param_id id, int val_ma, u8 *buf);

extern void fg_encode_default(struct fg_sram_param *sp,

	enum fg_sram_param_id id, int val, u8 *buf);

extern void fg_encode(struct fg_sram_param *sp,

	enum fg_sram_param_id id, int val, u8 *buf);

extern int fg_get_sram_prop(struct fg_dev *fg, enum fg_sram_param_id id,

	int *val);

extern int fg_get_msoc_raw(struct fg_dev *fg, int *val);

extern int fg_get_msoc(struct fg_dev *fg, int *val);

extern const char *fg_get_battery_type(struct fg_dev *fg);

extern int fg_get_battery_resistance(struct fg_dev *fg, int *val);

extern int fg_get_battery_voltage(struct fg_dev *fg, int *val);

extern int fg_get_battery_current(struct fg_dev *fg, int *val);

extern int fg_set_esr_timer(struct fg_dev *fg, int cycles_init, int cycles_max,

				bool charging, int flags);

extern int fg_set_constant_chg_voltage(struct fg_dev *fg, int volt_uv);

extern int fg_register_interrupts(struct fg_dev *fg, int size);

extern void fg_unregister_interrupts(struct fg_dev *fg, void *data, int size);

extern int fg_sram_write(struct fg_dev *fg, u16 address, u8 offset,

			u8 *val, int len, int flags);

extern int fg_sram_read(struct fg_chip *chip, u16 address, u8 offset,

extern int fg_sram_read(struct fg_dev *fg, u16 address, u8 offset,

			u8 *val, int len, int flags);

extern int fg_sram_masked_write(struct fg_chip *chip, u16 address, u8 offset,

extern int fg_sram_masked_write(struct fg_dev *fg, u16 address, u8 offset,

			u8 mask, u8 val, int flags);

extern int fg_interleaved_mem_read(struct fg_chip *chip, u16 address,

extern int fg_interleaved_mem_read(struct fg_dev *fg, u16 address,

			u8 offset, u8 *val, int len);

extern int fg_interleaved_mem_write(struct fg_chip *chip, u16 address,

extern int fg_interleaved_mem_write(struct fg_dev *fg, u16 address,

			u8 offset, u8 *val, int len, bool atomic_access);

extern int fg_direct_mem_read(struct fg_chip *chip, u16 address,

extern int fg_direct_mem_read(struct fg_dev *fg, u16 address,

			u8 offset, u8 *val, int len);

extern int fg_direct_mem_write(struct fg_chip *chip, u16 address,

extern int fg_direct_mem_write(struct fg_dev *fg, u16 address,

			u8 offset, u8 *val, int len, bool atomic_access);

extern int fg_read(struct fg_chip *chip, int addr, u8 *val, int len);

extern int fg_write(struct fg_chip *chip, int addr, u8 *val, int len);

extern int fg_masked_write(struct fg_chip *chip, int addr, u8 mask, u8 val);

extern int fg_dump_regs(struct fg_chip *chip);

extern int fg_ima_init(struct fg_chip *chip);

extern int fg_dma_init(struct fg_chip *chip);

extern int fg_clear_ima_errors_if_any(struct fg_chip *chip, bool check_hw_sts);

extern int fg_clear_dma_errors_if_any(struct fg_chip *chip);

extern int fg_debugfs_create(struct fg_chip *chip);

extern int fg_read(struct fg_dev *fg, int addr, u8 *val, int len);

extern int fg_write(struct fg_dev *fg, int addr, u8 *val, int len);

extern int fg_masked_write(struct fg_dev *fg, int addr, u8 mask, u8 val);

extern int fg_dump_regs(struct fg_dev *fg);

extern int fg_restart(struct fg_dev *fg, int wait_time_ms);

extern int fg_memif_init(struct fg_dev *fg);

extern int fg_clear_ima_errors_if_any(struct fg_dev *fg, bool check_hw_sts);

extern int fg_clear_dma_errors_if_any(struct fg_dev *fg);

extern int fg_debugfs_create(struct fg_dev *fg);

extern void fill_string(char *str, size_t str_len, u8 *buf, int buf_len);

extern void dump_sram(u8 *buf, int addr, int len);

extern int64_t twos_compliment_extend(int64_t val, int s_bit_pos);

extern s64 fg_float_decode(u16 val);

extern bool is_input_present(struct fg_chip *chip);

extern bool is_qnovo_en(struct fg_chip *chip);

extern bool usb_psy_initialized(struct fg_dev *fg);

extern bool dc_psy_initialized(struct fg_dev *fg);

extern bool batt_psy_initialized(struct fg_dev *fg);

extern bool pc_port_psy_initialized(struct fg_dev *fg);

extern void fg_notify_charger(struct fg_dev *fg);

extern bool is_input_present(struct fg_dev *fg);

extern bool is_qnovo_en(struct fg_dev *fg);

extern bool is_parallel_charger_available(struct fg_dev *fg);

extern void fg_circ_buf_add(struct fg_circ_buf *buf, int val);

extern void fg_circ_buf_clr(struct fg_circ_buf *buf);

extern int fg_circ_buf_avg(struct fg_circ_buf *buf, int *avg);

drivers/power/supply/qcom/fg-memif.c

+177 −151

File changed.

Preview size limit exceeded, changes collapsed.

drivers/power/supply/qcom/fg-reg.h

+85 −126
Original line number Diff line number Diff line 
/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.

/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -23,81 +23,23 @@ 
#define BATT_SOC_SLEEP_SHUTDOWN_STS(chip)	(chip->batt_soc_base + 0x08)

#define BATT_SOC_FG_MONOTONIC_SOC(chip)		(chip->batt_soc_base + 0x09)

#define BATT_SOC_FG_MONOTONIC_SOC_CP(chip)	(chip->batt_soc_base + 0x0A)

#define BATT_SOC_INT_RT_STS(chip)		(chip->batt_soc_base + 0x10)

#define BATT_SOC_EN_CTL(chip)			(chip->batt_soc_base + 0x46)

#define BATT_SOC_RESTART(chip)			(chip->batt_soc_base + 0x48)

#define BATT_SOC_STS_CLR(chip)			(chip->batt_soc_base + 0x4A)

#define BATT_SOC_LOW_PWR_CFG(chip)		(chip->batt_soc_base + 0x52)

#define BATT_SOC_LOW_PWR_STS(chip)		(chip->batt_soc_base + 0x56)



/* BATT_SOC_INT_RT_STS */

#define BATT_SOC_INT_RT_STS(chip)		(chip->batt_soc_base + 0x10)

#define SOC_READY_BIT				BIT(1)

#define MSOC_EMPTY_BIT				BIT(5)



/* BATT_SOC_EN_CTL */

#define BATT_SOC_EN_CTL(chip)			(chip->batt_soc_base + 0x46)

#define FG_ALGORITHM_EN_BIT			BIT(7)



/* BATT_SOC_RESTART */

#define BATT_SOC_RESTART(chip)			(chip->batt_soc_base + 0x48)

#define RESTART_GO_BIT				BIT(0)



#define BATT_SOC_STS_CLR(chip)			(chip->batt_soc_base + 0x4A)

#define BATT_SOC_LOW_PWR_CFG(chip)		(chip->batt_soc_base + 0x52)

#define BATT_SOC_LOW_PWR_STS(chip)		(chip->batt_soc_base + 0x56)



/* FG_BATT_INFO register definitions */

#define BATT_INFO_BATT_TEMP_STS(chip)		(chip->batt_info_base + 0x06)

#define BATT_INFO_SYS_BATT(chip)		(chip->batt_info_base + 0x07)

#define BATT_INFO_FG_STS(chip)			(chip->batt_info_base + 0x09)

#define BATT_INFO_INT_RT_STS(chip)		(chip->batt_info_base + 0x10)

#define BATT_INFO_BATT_REM_LATCH(chip)		(chip->batt_info_base + 0x4F)

#define BATT_INFO_BATT_TEMP_LSB(chip)		(chip->batt_info_base + 0x50)

#define BATT_INFO_BATT_TEMP_MSB(chip)		(chip->batt_info_base + 0x51)

#define BATT_INFO_BATT_TEMP_CFG(chip)		(chip->batt_info_base + 0x56)

#define BATT_INFO_BATT_TMPR_INTR(chip)		(chip->batt_info_base + 0x59)

#define BATT_INFO_THERM_C1(chip)		(chip->batt_info_base + 0x5C)

#define BATT_INFO_THERM_C2(chip)		(chip->batt_info_base + 0x5D)

#define BATT_INFO_THERM_C3(chip)		(chip->batt_info_base + 0x5E)

#define BATT_INFO_THERM_HALF_RANGE(chip)	(chip->batt_info_base + 0x5F)

#define BATT_INFO_JEITA_CTLS(chip)		(chip->batt_info_base + 0x61)

#define BATT_INFO_JEITA_TOO_COLD(chip)		(chip->batt_info_base + 0x62)

#define BATT_INFO_JEITA_COLD(chip)		(chip->batt_info_base + 0x63)

#define BATT_INFO_JEITA_HOT(chip)		(chip->batt_info_base + 0x64)

#define BATT_INFO_JEITA_TOO_HOT(chip)		(chip->batt_info_base + 0x65)



/* only for v1.1 */

#define BATT_INFO_ESR_CFG(chip)			(chip->batt_info_base + 0x69)

/* starting from v2.0 */

#define BATT_INFO_ESR_GENERAL_CFG(chip)		(chip->batt_info_base + 0x68)

#define BATT_INFO_ESR_PULL_DN_CFG(chip)		(chip->batt_info_base + 0x69)

#define BATT_INFO_ESR_FAST_CRG_CFG(chip)	(chip->batt_info_base + 0x6A)



#define BATT_INFO_BATT_MISS_CFG(chip)		(chip->batt_info_base + 0x6B)

#define BATT_INFO_WATCHDOG_COUNT(chip)		(chip->batt_info_base + 0x70)

#define BATT_INFO_WATCHDOG_CFG(chip)		(chip->batt_info_base + 0x71)

#define BATT_INFO_IBATT_SENSING_CFG(chip)	(chip->batt_info_base + 0x73)

#define BATT_INFO_QNOVO_CFG(chip)		(chip->batt_info_base + 0x74)

#define BATT_INFO_QNOVO_SCALER(chip)		(chip->batt_info_base + 0x75)



/* starting from v2.0 */

#define BATT_INFO_CRG_SERVICES(chip)		(chip->batt_info_base + 0x90)



/* Following LSB/MSB address are for v2.0 and above; v1.1 have them swapped */

#define BATT_INFO_VBATT_LSB(chip)		(chip->batt_info_base + 0xA0)

#define BATT_INFO_VBATT_MSB(chip)		(chip->batt_info_base + 0xA1)

#define BATT_INFO_IBATT_LSB(chip)		(chip->batt_info_base + 0xA2)

#define BATT_INFO_IBATT_MSB(chip)		(chip->batt_info_base + 0xA3)

#define BATT_INFO_ESR_LSB(chip)			(chip->batt_info_base + 0xA4)

#define BATT_INFO_ESR_MSB(chip)			(chip->batt_info_base + 0xA5)

#define BATT_INFO_VBATT_LSB_CP(chip)		(chip->batt_info_base + 0xA6)

#define BATT_INFO_VBATT_MSB_CP(chip)		(chip->batt_info_base + 0xA7)

#define BATT_INFO_IBATT_LSB_CP(chip)		(chip->batt_info_base + 0xA8)

#define BATT_INFO_IBATT_MSB_CP(chip)		(chip->batt_info_base + 0xA9)

#define BATT_INFO_ESR_LSB_CP(chip)		(chip->batt_info_base + 0xAA)

#define BATT_INFO_ESR_MSB_CP(chip)		(chip->batt_info_base + 0xAB)

#define BATT_INFO_VADC_LSB(chip)		(chip->batt_info_base + 0xAC)

#define BATT_INFO_VADC_MSB(chip)		(chip->batt_info_base + 0xAD)

#define BATT_INFO_IADC_LSB(chip)		(chip->batt_info_base + 0xAE)

#define BATT_INFO_IADC_MSB(chip)		(chip->batt_info_base + 0xAF)

#define BATT_INFO_TM_MISC(chip)			(chip->batt_info_base + 0xE5)

#define BATT_INFO_TM_MISC1(chip)		(chip->batt_info_base + 0xE6)



/* BATT_INFO_BATT_TEMP_STS */

#define JEITA_TOO_HOT_STS_BIT			BIT(7)

#define JEITA_HOT_STS_BIT			BIT(6)

#define JEITA_COLD_STS_BIT			BIT(5)
@@ -105,18 +47,18 @@ 
#define BATT_TEMP_DELTA_BIT			BIT(1)

#define BATT_TEMP_AVAIL_BIT			BIT(0)



/* BATT_INFO_SYS_BATT */

#define BATT_INFO_SYS_BATT(chip)		(chip->batt_info_base + 0x07)

#define BATT_REM_LATCH_STS_BIT			BIT(4)

#define BATT_MISSING_HW_BIT			BIT(2)

#define BATT_MISSING_ALG_BIT			BIT(1)

#define BATT_MISSING_CMP_BIT			BIT(0)



/* BATT_INFO_FG_STS */

#define BATT_INFO_FG_STS(chip)			(chip->batt_info_base + 0x09)

#define FG_WD_RESET_BIT				BIT(7)

/* This bit is not present in v1.1 */

#define FG_CRG_TRM_BIT				BIT(0)



/* BATT_INFO_INT_RT_STS */

#define BATT_INFO_INT_RT_STS(chip)		(chip->batt_info_base + 0x10)

#define BT_TMPR_DELTA_BIT			BIT(6)

#define WDOG_EXP_BIT				BIT(5)

#define BT_ATTN_BIT				BIT(4)
@@ -125,14 +67,16 @@ 
#define VBT_LOW_BIT				BIT(1)

#define VBT_PRD_DELTA_BIT			BIT(0)



/* BATT_INFO_INT_RT_STS */

#define BATT_INFO_BATT_REM_LATCH(chip)		(chip->batt_info_base + 0x4F)

#define BATT_REM_LATCH_CLR_BIT			BIT(7)



/* BATT_INFO_BATT_TEMP_LSB/MSB */

#define BATT_INFO_BATT_TEMP_LSB(chip)		(chip->batt_info_base + 0x50)

#define BATT_TEMP_LSB_MASK			GENMASK(7, 0)



#define BATT_INFO_BATT_TEMP_MSB(chip)		(chip->batt_info_base + 0x51)

#define BATT_TEMP_MSB_MASK			GENMASK(2, 0)



/* BATT_INFO_BATT_TEMP_CFG */

#define BATT_INFO_BATT_TEMP_CFG(chip)		(chip->batt_info_base + 0x56)

#define JEITA_TEMP_HYST_MASK			GENMASK(5, 4)

#define JEITA_TEMP_HYST_SHIFT			4

#define JEITA_TEMP_NO_HYST			0x0
@@ -140,33 +84,42 @@ 
#define JEITA_TEMP_HYST_2C			0x2

#define JEITA_TEMP_HYST_3C			0x3



/* BATT_INFO_BATT_TMPR_INTR */

#define BATT_INFO_BATT_TMPR_INTR(chip)		(chip->batt_info_base + 0x59)

#define CHANGE_THOLD_MASK			GENMASK(1, 0)

#define BTEMP_DELTA_2K				0x0

#define BTEMP_DELTA_4K				0x1

#define BTEMP_DELTA_6K				0x2

#define BTEMP_DELTA_10K				0x3



/* BATT_INFO_THERM_C1/C2/C3 */

#define BATT_INFO_THERM_C1(chip)		(chip->batt_info_base + 0x5C)

#define BATT_INFO_THERM_COEFF_MASK		GENMASK(7, 0)



/* BATT_INFO_THERM_HALF_RANGE */

#define BATT_INFO_THERM_C2(chip)		(chip->batt_info_base + 0x5D)

#define BATT_INFO_THERM_C3(chip)		(chip->batt_info_base + 0x5E)



#define BATT_INFO_THERM_HALF_RANGE(chip)	(chip->batt_info_base + 0x5F)

#define BATT_INFO_THERM_TEMP_MASK		GENMASK(7, 0)



/* BATT_INFO_JEITA_CTLS */

#define BATT_INFO_JEITA_CTLS(chip)		(chip->batt_info_base + 0x61)

#define JEITA_STS_CLEAR_BIT			BIT(0)



/* BATT_INFO_JEITA_TOO_COLD/COLD/HOT/TOO_HOT */

#define BATT_INFO_JEITA_TOO_COLD(chip)		(chip->batt_info_base + 0x62)

#define JEITA_THOLD_MASK			GENMASK(7, 0)



/* BATT_INFO_ESR_CFG */

#define BATT_INFO_JEITA_COLD(chip)		(chip->batt_info_base + 0x63)

#define BATT_INFO_JEITA_HOT(chip)		(chip->batt_info_base + 0x64)

#define BATT_INFO_JEITA_TOO_HOT(chip)		(chip->batt_info_base + 0x65)



/* only for v1.1 */

#define BATT_INFO_ESR_CFG(chip)			(chip->batt_info_base + 0x69)

#define CFG_ACTIVE_PD_MASK			GENMASK(2, 1)

#define CFG_FCC_DEC_MASK			GENMASK(4, 3)



/* BATT_INFO_ESR_GENERAL_CFG */

/* starting from v2.0 */

#define BATT_INFO_ESR_GENERAL_CFG(chip)		(chip->batt_info_base + 0x68)

#define ESR_DEEP_TAPER_EN_BIT			BIT(0)



/* BATT_INFO_ESR_PULL_DN_CFG */

#define BATT_INFO_ESR_PULL_DN_CFG(chip)		(chip->batt_info_base + 0x69)

#define ESR_PULL_DOWN_IVAL_MASK			GENMASK(3, 2)

#define ESR_PULL_DOWN_IVAL_SHIFT		2

#define ESR_MEAS_CUR_60MA			0x0
@@ -179,7 +132,7 @@ 
#define ESR_CRG_DSC_PULL_DOWN			0x2

#define ESR_DSC_PULL_DOWN			0x3



/* BATT_INFO_ESR_FAST_CRG_CFG */

#define BATT_INFO_ESR_FAST_CRG_CFG(chip)	(chip->batt_info_base + 0x6A)

#define ESR_FAST_CRG_IVAL_MASK			GENMASK(3, 1)

#define ESR_FCC_300MA				0x0

#define ESR_FCC_600MA				0x1
@@ -191,7 +144,7 @@ 
#define ESR_FCC_6A				0x7

#define ESR_FAST_CRG_CTL_EN_BIT			BIT(0)



/* BATT_INFO_BATT_MISS_CFG */

#define BATT_INFO_BATT_MISS_CFG(chip)		(chip->batt_info_base + 0x6B)

#define BM_THERM_TH_MASK			GENMASK(5, 4)

#define RES_TH_0P75_MOHM			0x0

#define RES_TH_1P00_MOHM			0x1
@@ -201,22 +154,22 @@ 
#define BM_FROM_THERM_BIT			BIT(1)

#define BM_FROM_BATT_ID_BIT			BIT(0)



/* BATT_INFO_WATCHDOG_COUNT */

#define BATT_INFO_WATCHDOG_COUNT(chip)		(chip->batt_info_base + 0x70)

#define WATCHDOG_COUNTER			GENMASK(7, 0)



/* BATT_INFO_WATCHDOG_CFG */

#define BATT_INFO_WATCHDOG_CFG(chip)		(chip->batt_info_base + 0x71)

#define RESET_CAPABLE_BIT			BIT(2)

#define PET_CTRL_BIT				BIT(1)

#define ENABLE_CTRL_BIT				BIT(0)



/* BATT_INFO_IBATT_SENSING_CFG */

#define BATT_INFO_IBATT_SENSING_CFG(chip)	(chip->batt_info_base + 0x73)

#define ADC_BITSTREAM_INV_BIT			BIT(4)

#define SOURCE_SELECT_MASK			GENMASK(1, 0)

#define SRC_SEL_BATFET				0x0

#define SRC_SEL_BATFET_SMB			0x2

#define SRC_SEL_RESERVED			0x3



/* BATT_INFO_QNOVO_CFG */

#define BATT_INFO_QNOVO_CFG(chip)		(chip->batt_info_base + 0x74)

#define LD_REG_FORCE_CTL_BIT			BIT(2)

#define LD_REG_CTRL_FORCE_HIGH			LD_REG_FORCE_CTL_BIT

#define LD_REG_CTRL_FORCE_LOW			0
@@ -225,31 +178,47 @@ 
#define LD_REG_CTRL_LOGIC			0

#define BIT_STREAM_CFG_BIT			BIT(0)



/* BATT_INFO_QNOVO_SCALER */

#define BATT_INFO_QNOVO_SCALER(chip)		(chip->batt_info_base + 0x75)

#define QNOVO_SCALER_MASK			GENMASK(7, 0)



/* BATT_INFO_CRG_SERVICES */

/* starting from v2.0 */

#define BATT_INFO_CRG_SERVICES(chip)		(chip->batt_info_base + 0x90)

#define FG_CRC_TRM_EN_BIT			BIT(0)



/* BATT_INFO_VBATT_LSB/MSB */

/* Following LSB/MSB address are for v2.0 and above; v1.1 have them swapped */

#define BATT_INFO_VBATT_LSB(chip)		(chip->batt_info_base + 0xA0)

#define BATT_INFO_VBATT_MSB(chip)		(chip->batt_info_base + 0xA1)

#define VBATT_MASK				GENMASK(7, 0)



/* BATT_INFO_IBATT_LSB/MSB */

#define BATT_INFO_IBATT_LSB(chip)		(chip->batt_info_base + 0xA2)

#define BATT_INFO_IBATT_MSB(chip)		(chip->batt_info_base + 0xA3)

#define IBATT_MASK				GENMASK(7, 0)



/* BATT_INFO_ESR_LSB/MSB */

#define BATT_INFO_ESR_LSB(chip)			(chip->batt_info_base + 0xA4)

#define BATT_INFO_ESR_MSB(chip)			(chip->batt_info_base + 0xA5)

#define ESR_LSB_MASK				GENMASK(7, 0)

#define ESR_MSB_MASK				GENMASK(5, 0)



/* BATT_INFO_VADC_LSB/MSB */

#define BATT_INFO_VBATT_LSB_CP(chip)		(chip->batt_info_base + 0xA6)

#define BATT_INFO_VBATT_MSB_CP(chip)		(chip->batt_info_base + 0xA7)

#define BATT_INFO_IBATT_LSB_CP(chip)		(chip->batt_info_base + 0xA8)

#define BATT_INFO_IBATT_MSB_CP(chip)		(chip->batt_info_base + 0xA9)

#define BATT_INFO_ESR_LSB_CP(chip)		(chip->batt_info_base + 0xAA)

#define BATT_INFO_ESR_MSB_CP(chip)		(chip->batt_info_base + 0xAB)



#define BATT_INFO_VADC_LSB(chip)		(chip->batt_info_base + 0xAC)

#define VADC_LSB_MASK				GENMASK(7, 0)



#define BATT_INFO_VADC_MSB(chip)		(chip->batt_info_base + 0xAD)

#define VADC_MSB_MASK				GENMASK(6, 0)



/* BATT_INFO_IADC_LSB/MSB */

#define BATT_INFO_IADC_LSB(chip)		(chip->batt_info_base + 0xAE)

#define IADC_LSB_MASK				GENMASK(7, 0)



#define BATT_INFO_IADC_MSB(chip)		(chip->batt_info_base + 0xAF)

#define IADC_MSB_MASK				GENMASK(6, 0)



/* BATT_INFO_TM_MISC */

#define BATT_INFO_TM_MISC(chip)			(chip->batt_info_base + 0xE5)

#define FORCE_SEQ_RESP_TOGGLE_BIT		BIT(6)

#define ALG_DIRECT_VALID_DATA_BIT		BIT(5)

#define ALG_DIRECT_MODE_EN_BIT			BIT(4)
@@ -260,58 +229,38 @@ 
/* only for v1.1 */

#define ESR_PULSE_FORCE_CTRL_BIT		BIT(7)



/* BATT_INFO_TM_MISC1 */

#define BATT_INFO_TM_MISC1(chip)		(chip->batt_info_base + 0xE6)

/* for v2.0 and above */

#define ESR_REQ_CTL_BIT				BIT(1)

#define ESR_REQ_CTL_EN_BIT			BIT(0)



/* FG_MEM_IF register and bit definitions */

#define MEM_IF_INT_RT_STS(chip)			((chip->mem_if_base) + 0x10)

#define MEM_IF_MEM_ARB_CFG(chip)		((chip->mem_if_base) + 0x40)

#define MEM_IF_MEM_INTF_CFG(chip)		((chip->mem_if_base) + 0x50)

#define MEM_IF_IMA_CTL(chip)			((chip->mem_if_base) + 0x51)

#define MEM_IF_IMA_CFG(chip)			((chip->mem_if_base) + 0x52)

#define MEM_IF_IMA_OPR_STS(chip)		((chip->mem_if_base) + 0x54)

#define MEM_IF_IMA_EXP_STS(chip)		((chip->mem_if_base) + 0x55)

#define MEM_IF_IMA_HW_STS(chip)			((chip->mem_if_base) + 0x56)

#define MEM_IF_FG_BEAT_COUNT(chip)		((chip->mem_if_base) + 0x57)

#define MEM_IF_IMA_ERR_STS(chip)		((chip->mem_if_base) + 0x5F)

#define MEM_IF_IMA_BYTE_EN(chip)		((chip->mem_if_base) + 0x60)

#define MEM_IF_ADDR_LSB(chip)			((chip->mem_if_base) + 0x61)

#define MEM_IF_ADDR_MSB(chip)			((chip->mem_if_base) + 0x62)

#define MEM_IF_WR_DATA0(chip)			((chip->mem_if_base) + 0x63)

#define MEM_IF_WR_DATA3(chip)			((chip->mem_if_base) + 0x66)

#define MEM_IF_RD_DATA0(chip)			((chip->mem_if_base) + 0x67)

#define MEM_IF_RD_DATA3(chip)			((chip->mem_if_base) + 0x6A)

#define MEM_IF_DMA_STS(chip)			((chip->mem_if_base) + 0x70)

#define MEM_IF_DMA_CTL(chip)			((chip->mem_if_base) + 0x71)



/* MEM_IF_INT_RT_STS */

#define MEM_XCP_BIT				BIT(1)

#define MEM_GNT_BIT				BIT(2)



/* MEM_IF_MEM_ARB_CFG */

#define MEM_IF_MEM_ARB_CFG(chip)		((chip->mem_if_base) + 0x40)

#define MEM_ARB_LO_LATENCY_EN_BIT		BIT(1)

#define MEM_ARB_REQ_BIT				BIT(0)



/* MEM_IF_MEM_INTF_CFG */

#define MEM_IF_MEM_INTF_CFG(chip)		((chip->mem_if_base) + 0x50)

#define MEM_ACCESS_REQ_BIT			BIT(7)

#define IACS_SLCT_BIT				BIT(5)



/* MEM_IF_IMA_CTL */

#define MEM_IF_IMA_CTL(chip)			((chip->mem_if_base) + 0x51)

#define MEM_ACS_BURST_BIT			BIT(7)

#define IMA_WR_EN_BIT				BIT(6)

#define IMA_CTL_MASK				GENMASK(7, 6)



/* MEM_IF_IMA_CFG */

#define MEM_IF_IMA_CFG(chip)			((chip->mem_if_base) + 0x52)

#define IACS_CLR_BIT				BIT(2)

#define IACS_INTR_SRC_SLCT_BIT			BIT(3)

#define STATIC_CLK_EN_BIT			BIT(4)



/* MEM_IF_IMA_OPR_STS */

#define MEM_IF_IMA_OPR_STS(chip)		((chip->mem_if_base) + 0x54)

#define IACS_RDY_BIT				BIT(1)



/* MEM_IF_IMA_EXP_STS */

#define MEM_IF_IMA_EXP_STS(chip)		((chip->mem_if_base) + 0x55)

#define IACS_ERR_BIT				BIT(0)

#define XCT_TYPE_ERR_BIT			BIT(1)

#define DATA_RD_ERR_BIT				BIT(3)
@@ -319,19 +268,29 @@ 
#define ADDR_BURST_WRAP_BIT			BIT(5)

#define ADDR_STABLE_ERR_BIT			BIT(7)



/* MEM_IF_IMA_ERR_STS */

#define MEM_IF_IMA_HW_STS(chip)			((chip->mem_if_base) + 0x56)



#define MEM_IF_FG_BEAT_COUNT(chip)		((chip->mem_if_base) + 0x57)

#define BEAT_COUNT_MASK				GENMASK(3, 0)



#define MEM_IF_IMA_ERR_STS(chip)		((chip->mem_if_base) + 0x5F)

#define ADDR_STBL_ERR_BIT			BIT(7)

#define WR_ACS_ERR_BIT				BIT(6)

#define RD_ACS_ERR_BIT				BIT(5)



/* MEM_IF_FG_BEAT_COUNT */

#define BEAT_COUNT_MASK				GENMASK(3, 0)

#define MEM_IF_IMA_BYTE_EN(chip)		((chip->mem_if_base) + 0x60)

#define MEM_IF_ADDR_LSB(chip)			((chip->mem_if_base) + 0x61)

#define MEM_IF_ADDR_MSB(chip)			((chip->mem_if_base) + 0x62)

#define MEM_IF_WR_DATA0(chip)			((chip->mem_if_base) + 0x63)

#define MEM_IF_WR_DATA3(chip)			((chip->mem_if_base) + 0x66)

#define MEM_IF_RD_DATA0(chip)			((chip->mem_if_base) + 0x67)

#define MEM_IF_RD_DATA3(chip)			((chip->mem_if_base) + 0x6A)



/* MEM_IF_DMA_STS */

#define MEM_IF_DMA_STS(chip)			((chip->mem_if_base) + 0x70)

#define DMA_WRITE_ERROR_BIT			BIT(1)

#define DMA_READ_ERROR_BIT			BIT(2)



/* MEM_IF_DMA_CTL */

#define MEM_IF_DMA_CTL(chip)			((chip->mem_if_base) + 0x71)

#define ADDR_KIND_BIT				BIT(1)

#define DMA_CLEAR_LOG_BIT			BIT(0)

drivers/power/supply/qcom/fg-util.c

+713 −149

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drivers/power/supply/qcom/qpnp-fg-gen3.c

+953 −1407

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