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Commit 0c92b969 authored by Jack Pham's avatar Jack Pham
Browse files

ARM: dts: msm: Update USB QMP DP PHY init sequence on SM8150 



Update USB QMP DP PHY initialization sequence (version 2.5) for USB
SSP functionality on SM8150.

Change-Id: I47031c9d1decea6701ef57db5824b68ed481434c
Signed-off-by: default avatarJack Pham <jackp@codeaurora.org>
parent 76f60b6d

arch/arm64/boot/dts/qcom/sm8150-usb.dtsi

+6 −6
Original line number Diff line number Diff line
@@ -212,10 +212,10 @@ 
		     USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04 0

		     USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0e 0

		     USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0x3f 0

		     USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0xbf 0

		     USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0x3f 0

		     USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x7f 0

		     USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0x7f 0

		     USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x3f 0

		     USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0x8a 0

		     USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0xa4 0

		     USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0xdc 0

		     USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0xdc 0

		     USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0x5c 0
@@ -250,10 +250,10 @@ 
		     USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04 0

		     USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0e 0

		     USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0x3f 0

		     USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0xbf 0

		     USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0x3f 0

		     USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0x7f 0

		     USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0x7f 0

		     USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x3f 0

		     USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0x8a 0

		     USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xa4 0

		     USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0xdc 0

		     USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0xdc 0

		     USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x5c 0