Merge "Merge remote-tracking branch 'quic/dev/msm-4.14-display' into msm-4.14" (0c55f433) · Commits · e / devices / android_kernel_oneplus_sm8150

arch/arm64/boot/dts/qcom/dsi-panel-hx83112a-truly-singlemipi-fhd-video.dtsi

0 → 100644

+157 −0

Original line number	Diff line number	Diff line
		/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		* only version 2 as published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*/

		&mdss_mdp {
		dsi_hx83112a_truly_video: qcom,mdss_dsi_hx83112a_truly_video {
		qcom,mdss-dsi-panel-name =
		"hx83112a video mode dsi truly panel";
		qcom,mdss-dsi-panel-type = "dsi_video_mode";

		qcom,mdss-dsi-virtual-channel-id = <0>;
		qcom,mdss-dsi-stream = <0>;
		qcom,mdss-dsi-h-left-border = <0>;
		qcom,mdss-dsi-h-right-border = <0>;
		qcom,mdss-dsi-v-top-border = <0>;
		qcom,mdss-dsi-v-bottom-border = <0>;
		qcom,mdss-dsi-bpp = <24>;
		qcom,mdss-dsi-color-order = "rgb_swap_rgb";
		qcom,mdss-dsi-underflow-color = <0xff>;
		qcom,mdss-dsi-border-color = <0>;
		qcom,mdss-dsi-h-sync-pulse = <0>;
		qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
		qcom,mdss-dsi-lane-map = "lane_map_0123";
		qcom,mdss-dsi-bllp-eof-power-mode;
		qcom,mdss-dsi-bllp-power-mode;
		qcom,mdss-dsi-tx-eot-append;
		qcom,mdss-dsi-lane-0-state;
		qcom,mdss-dsi-lane-1-state;
		qcom,mdss-dsi-lane-2-state;
		qcom,mdss-dsi-lane-3-state;
		qcom,mdss-dsi-dma-trigger = "trigger_sw";
		qcom,mdss-dsi-mdp-trigger = "none";
		qcom,mdss-dsi-lp11-init;
		qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
		qcom,mdss-dsi-bl-min-level = <1>;
		qcom,mdss-dsi-bl-max-level = <4095>;
		qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;

		qcom,mdss-dsi-display-timings {
		timing@0 {
		qcom,mdss-dsi-panel-width = <1080>;
		qcom,mdss-dsi-panel-height = <2160>;
		qcom,mdss-dsi-h-front-porch = <42>;
		qcom,mdss-dsi-h-back-porch = <42>;
		qcom,mdss-dsi-h-pulse-width = <10>;
		qcom,mdss-dsi-h-sync-skew = <0>;
		qcom,mdss-dsi-v-back-porch = <15>;
		qcom,mdss-dsi-v-front-porch = <10>;
		qcom,mdss-dsi-v-pulse-width = <3>;
		qcom,mdss-dsi-panel-framerate = <60>;
		qcom,mdss-dsi-on-command = [
		39 01 00 00 00 00 04 B9 83 11 2A
		39 01 00 00 00 00 09 B1 08 29 29 00 00 4F 54
		33
		39 01 00 00 00 00 11 B2 00 02 00 80 70 00 08
		26 FC 01 00 03 15 A3 87 09
		39 01 00 00 00 00 02 BD 02
		39 01 00 00 00 00 02 BD 00
		39 01 00 00 00 00 03 D2 2C 2C
		39 01 00 00 00 00 1C B4 01 CE 01 CE 01 CE 0A
		CE 0A CE 0A CE 00 FF 00 FF 00 00 22 23 00
		28 0A 13 14 00 8A
		39 01 00 00 00 00 02 BD 02
		39 01 00 00 00 00 0A B4 00 92 12 22 88 12 12
		00 53
		39 01 00 00 00 00 02 BD 00
		39 01 00 00 00 00 04 B6 82 82 E3
		39 01 00 00 00 00 02 CC 08
		39 01 00 00 00 00 2B D3 40 00 00 00 00 01 01
		0A 0A 07 07 00 08 09 09 09 09 32 10 09 00
		09 32 21 0A 00 0A 32 10 08 00 00 00 00 00
		00 00 00 00 0B 08 82
		39 01 00 00 00 00 02 BD 01
		39 01 00 00 00 00 09 D3 00 00 19 00 00 0A 00
		81
		39 01 00 00 00 00 02 BD 00
		39 01 00 00 00 00 31 D5 18 18 18 18 18 18 18
		18 31 31 30 30 2F 2F 31 31 30 30 2F 2F C0
		18 40 40 01 00 07 06 05 04 03 02 21 20 18
		18 19 19 18 18 03 03 18 18 18 18 18 18
		39 01 00 00 00 00 31 D6 18 18 18 18 18 18 18
		18 31 31 30 30 2F 2F 31 31 30 30 2F 2F C0
		18 40 40 02 03 04 05 06 07 00 01 20 21 18
		18 18 18 19 19 20 20 18 18 18 18 18 18
		39 01 00 00 00 00 19 D8 00 00 00 00 00 00 00
		00 00 00 00 00 00 00 00 00 00 00 00 00 00
		00 00 00
		39 01 00 00 00 00 02 BD 01
		39 01 00 00 00 00 19 D8 AA AA AA AA AA AA AA
		AA AA AA AA AA AA AA AA AA AA AA AA AA AA
		AA AA AA
		39 01 00 00 00 00 02 BD 02
		39 01 00 00 00 00 0D D8 AF FF FA AA BA AA AA
		FF FA AA BA AA
		39 01 00 00 00 00 02 BD 03
		39 01 00 00 00 00 19 D8 AA AA AA AA AA AA AA
		AA AA AA AA AA AA AA AA AA AA AA AA AA AA
		AA AA AA
		39 01 00 00 00 00 02 BD 00
		39 01 00 00 00 00 18 E7 0E 0E 1E 6A 1D 6A 00
		32 02 02 00 00 02 02 02 05 14 14 32 B9 23
		B9 08
		39 01 00 00 00 00 02 BD 01
		39 01 00 00 00 00 0A E7 02 00 98 01 9A 0D A8
		0E 01
		39 01 00 00 00 00 02 BD 02
		39 01 00 00 00 00 1E E7 00 00 08 00 01 00 00
		00 00 00 00 00 00 00 00 00 00 00 00 00 00
		00 04 00 00 00 00 02 00
		39 01 00 00 00 00 02 BD 00
		39 01 00 00 00 00 02 C1 01
		39 01 00 00 00 00 02 BD 01
		39 01 00 00 00 00 3A C1 FF F7 F0 E9 E2 DB D4
		C6 BF B8 B1 AB A5 9F 99 94 8E 8A 85 7C 74
		6C 65 5F 58 52 4B 47 42 3C 37 31 2C 27 22
		1C 18 12 0D 08 05 04 02 01 00 27 B9 BE 54
		C6 B8 9C 37 43 3D E5 00
		39 01 00 00 00 00 02 BD 02
		39 01 00 00 00 00 3A C1 FF F7 F0 E9 E2 DB D4
		C6 BF B8 B1 AB A5 9F 99 94 8E 8A 85 7C 74
		6C 65 5F 58 52 4B 47 42 3C 37 31 2C 27 22
		1C 18 12 0D 08 05 04 02 01 00 27 B9 BE 54
		C6 B8 9C 37 43 3D E5 00
		39 01 00 00 00 00 02 BD 03
		39 01 00 00 00 00 3A C1 FF F7 F0 E9 E2 DB D4
		C6 BF B8 B1 AB A5 9F 99 94 8E 8A 85 7C 74
		6C 65 5F 58 52 4B 47 42 3C 37 31 2C 27 22
		1C 18 12 0D 08 05 04 02 01 00 27 B9 BE 54
		C6 B8 9C 37 43 3D E5 00
		39 01 00 00 00 00 02 BD 00
		39 01 00 00 00 00 02 E9 C3
		39 01 00 00 00 00 03 CB 92 01
		39 01 00 00 00 00 02 E9 3F
		39 01 00 00 00 00 07 C7 70 00 04 E0 33 00
		39 01 00 00 00 00 03 51 0F FF
		39 01 00 00 00 00 02 53 24
		39 01 00 00 00 00 02 55 00
		15 01 00 00 00 00 02 35 00
		05 01 00 00 96 00 02 11 00
		05 01 00 00 32 00 02 29 00];
		qcom,mdss-dsi-off-command = [
		05 01 00 00 32 00 02 28 00
		05 01 00 00 96 00 02 10 00];
		qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
		qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
		};
		};
		};
		};

arch/arm64/boot/dts/qcom/sm8150-sde-display.dtsi

+3 −3

Original line number	Diff line number	Diff line
		@@ -652,7 +652,7 @@
		timing@0{
		qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
		07 05 02 04 00 18 17];
		qcom,display-topology = <1 0 1>,
		qcom,display-topology = <1 1 1>,
		<2 2 1>;
		qcom,default-topology-index = <1>;
		qcom,panel-roi-alignment = <720 40 720 40 720 40>;
		@@ -662,7 +662,7 @@
		timing@1{
		qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
		07 05 02 04 00 18 17];
		qcom,display-topology = <1 0 1>,
		qcom,display-topology = <1 1 1>,
		<2 2 1>;
		qcom,default-topology-index = <1>;
		qcom,panel-roi-alignment = <540 40 540 40 540 40>;
		@@ -672,7 +672,7 @@
		timing@2{
		qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
		07 05 02 04 00 18 17];
		qcom,display-topology = <1 0 1>,
		qcom,display-topology = <1 1 1>,
		<2 2 1>;
		qcom,default-topology-index = <1>;
		qcom,panel-roi-alignment = <360 40 360 40 360 40>;

drivers/gpu/drm/msm/dp/dp_debug.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -801,7 +801,7 @@ static ssize_t dp_debug_write_hdr(struct file *file,
		struct sde_connector *c_conn;
		struct sde_connector_state *c_state;
		struct dp_debug_private *debug = file->private_data;
		char buf[SZ_1K];
		char buf[SZ_512];
		size_t len = 0;

		if (!debug)
		@@ -815,7 +815,7 @@ static ssize_t dp_debug_write_hdr(struct file *file,
		c_state = to_sde_connector_state(connector->state);

		/* Leave room for termination char */
		len = min_t(size_t, count, SZ_1K - 1);
		len = min_t(size_t, count, SZ_512 - 1);
		if (copy_from_user(buf, user_buff, len))
		goto end;

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h

+4 −8

Original line number	Diff line number	Diff line
		@@ -161,7 +161,7 @@ enum dsi_status_int_type {
		* @DSI_EINT_DLN0_ESC_ENTRY_ERR: Incorrect LP Rx escape entry.
		* @DSI_EINT_DLN0_ESC_SYNC_ERR: LP Rx data is not byte aligned.
		* @DSI_EINT_DLN0_LP_CONTROL_ERR: Incorrect LP Rx state sequence.
		* @DSI_EINT_PENDING_HS_TX_TIMEOUT: Pending High-speed transfer timeout.
		* @DSI_EINT_PANEL_SPECIFIC_ERR: DSI Protocol violation error.
		* @DSI_EINT_INTERLEAVE_OP_CONTENTION: Interleave operation contention.
		* @DSI_EINT_CMD_DMA_FIFO_UNDERFLOW: Command mode DMA FIFO underflow.
		* @DSI_EINT_CMD_MDP_FIFO_UNDERFLOW: Command MDP FIFO underflow (failed to
		@@ -182,7 +182,6 @@ enum dsi_status_int_type {
		* @DSI_EINT_DLN1_LP1_CONTENTION: PHY level contention while lane 1 high.
		* @DSI_EINT_DLN2_LP1_CONTENTION: PHY level contention while lane 2 high.
		* @DSI_EINT_DLN3_LP1_CONTENTION: PHY level contention while lane 3 high.
		* @DSI_EINT_PANEL_SPECIFIC_ERR: DSI Protocol violation error.
		*/
		enum dsi_error_int_index {
		DSI_EINT_RDBK_SINGLE_ECC_ERR = 0,
		@@ -197,7 +196,7 @@ enum dsi_error_int_index {
		DSI_EINT_DLN0_ESC_ENTRY_ERR = 9,
		DSI_EINT_DLN0_ESC_SYNC_ERR = 10,
		DSI_EINT_DLN0_LP_CONTROL_ERR = 11,
		DSI_EINT_PENDING_HS_TX_TIMEOUT = 12,
		DSI_EINT_PANEL_SPECIFIC_ERR = 12,
		DSI_EINT_INTERLEAVE_OP_CONTENTION = 13,
		DSI_EINT_CMD_DMA_FIFO_UNDERFLOW = 14,
		DSI_EINT_CMD_MDP_FIFO_UNDERFLOW = 15,
		@@ -217,7 +216,6 @@ enum dsi_error_int_index {
		DSI_EINT_DLN1_LP1_CONTENTION = 29,
		DSI_EINT_DLN2_LP1_CONTENTION = 30,
		DSI_EINT_DLN3_LP1_CONTENTION = 31,
		DSI_EINT_PANEL_SPECIFIC_ERR = 32,

		DSI_ERROR_INTERRUPT_COUNT
		};
		@@ -236,7 +234,7 @@ enum dsi_error_int_index {
		* @DSI_DLN0_ESC_ENTRY_ERR: Incorrect LP Rx escape entry.
		* @DSI_DLN0_ESC_SYNC_ERR: LP Rx data is not byte aligned.
		* @DSI_DLN0_LP_CONTROL_ERR: Incorrect LP Rx state sequence.
		* @DSI_PENDING_HS_TX_TIMEOUT: Pending High-speed transfer timeout.
		* @DSI_PANEL_SPECIFIC_ERR: DSI Protocol violation.
		* @DSI_INTERLEAVE_OP_CONTENTION: Interleave operation contention.
		* @DSI_CMD_DMA_FIFO_UNDERFLOW: Command mode DMA FIFO underflow.
		* @DSI_CMD_MDP_FIFO_UNDERFLOW: Command MDP FIFO underflow (failed to
		@@ -257,7 +255,6 @@ enum dsi_error_int_index {
		* @DSI_DLN1_LP1_CONTENTION: PHY level contention while lane 1 is high.
		* @DSI_DLN2_LP1_CONTENTION: PHY level contention while lane 2 is high.
		* @DSI_DLN3_LP1_CONTENTION: PHY level contention while lane 3 is high.
		* @DSI_PANEL_SPECIFIC_ERR: DSI Protocol violation.
		*/
		enum dsi_error_int_type {
		DSI_RDBK_SINGLE_ECC_ERR = BIT(DSI_EINT_RDBK_SINGLE_ECC_ERR),
		@@ -272,7 +269,7 @@ enum dsi_error_int_type {
		DSI_DLN0_ESC_ENTRY_ERR = BIT(DSI_EINT_DLN0_ESC_ENTRY_ERR),
		DSI_DLN0_ESC_SYNC_ERR = BIT(DSI_EINT_DLN0_ESC_SYNC_ERR),
		DSI_DLN0_LP_CONTROL_ERR = BIT(DSI_EINT_DLN0_LP_CONTROL_ERR),
		DSI_PENDING_HS_TX_TIMEOUT = BIT(DSI_EINT_PENDING_HS_TX_TIMEOUT),
		DSI_PANEL_SPECIFIC_ERR = BIT(DSI_EINT_PANEL_SPECIFIC_ERR),
		DSI_INTERLEAVE_OP_CONTENTION = BIT(DSI_EINT_INTERLEAVE_OP_CONTENTION),
		DSI_CMD_DMA_FIFO_UNDERFLOW = BIT(DSI_EINT_CMD_DMA_FIFO_UNDERFLOW),
		DSI_CMD_MDP_FIFO_UNDERFLOW = BIT(DSI_EINT_CMD_MDP_FIFO_UNDERFLOW),
		@@ -292,7 +289,6 @@ enum dsi_error_int_type {
		DSI_DLN1_LP1_CONTENTION = BIT(DSI_EINT_DLN1_LP1_CONTENTION),
		DSI_DLN2_LP1_CONTENTION = BIT(DSI_EINT_DLN2_LP1_CONTENTION),
		DSI_DLN3_LP1_CONTENTION = BIT(DSI_EINT_DLN3_LP1_CONTENTION),
		DSI_PANEL_SPECIFIC_ERR = BIT(DSI_EINT_PANEL_SPECIFIC_ERR),
		};

		/**

drivers/gpu/drm/msm/dsi-staging/dsi_display.c

+20 −5

Original line number	Diff line number	Diff line
		@@ -801,7 +801,7 @@ static int dsi_display_cmd_prepare(const char *cmd_buf, u32 cmd_buf_len,
		cmd->msg.tx_len = ((cmd_buf[5] << 8) \| (cmd_buf[6]));

		if (cmd->msg.tx_len > payload_len) {
		pr_err("Incorrect payload length tx_len %ld, payload_len %d\n",
		pr_err("Incorrect payload length tx_len %zu, payload_len %d\n",
		cmd->msg.tx_len, payload_len);
		return -EINVAL;
		}
		@@ -1200,6 +1200,7 @@ static ssize_t debugfs_esd_trigger_check(struct file *file,
		display->esd_trigger = esd_trigger;

		if (display->esd_trigger) {
		pr_info("ESD attack triggered by user\n");
		rc = dsi_panel_trigger_esd_attack(display->panel);
		if (rc) {
		pr_err("Failed to trigger ESD attack\n");
		@@ -1256,11 +1257,13 @@ static ssize_t debugfs_alter_esd_check_mode(struct file *file,
		goto error;

		if (!strcmp(buf, "te_signal_check\n")) {
		pr_info("ESD check is switched to TE mode by user\n");
		esd_config->status_mode = ESD_MODE_PANEL_TE;
		dsi_display_change_te_irq_status(display, true);
		}

		if (!strcmp(buf, "reg_read\n")) {
		pr_info("ESD check is switched to reg read by user\n");
		rc = dsi_panel_parse_esd_reg_read_configs(display->panel);
		if (rc) {
		pr_err("failed to alter esd check mode,rc=%d\n",
		@@ -1323,11 +1326,23 @@ static ssize_t debugfs_read_esd_check_mode(struct file *file,
		goto output_mode;
		}

		if (esd_config->status_mode == ESD_MODE_REG_READ)
		switch (esd_config->status_mode) {
		case ESD_MODE_REG_READ:
		rc = snprintf(buf, len, "reg_read");

		if (esd_config->status_mode == ESD_MODE_PANEL_TE)
		break;
		case ESD_MODE_PANEL_TE:
		rc = snprintf(buf, len, "te_signal_check");
		break;
		case ESD_MODE_SW_SIM_FAILURE:
		rc = snprintf(buf, len, "esd_sw_sim_failure");
		break;
		case ESD_MODE_SW_SIM_SUCCESS:
		rc = snprintf(buf, len, "esd_sw_sim_success");
		break;
		default:
		rc = snprintf(buf, len, "invalid");
		break;
		}

		output_mode:
		if (!rc) {