Loading arch/arm64/configs/vendor/sa8155_defconfig +2 −0 Original line number Diff line number Diff line Loading @@ -86,6 +86,8 @@ CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y CONFIG_BUILD_ARM64_UNCOMPRESSED_KERNEL=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_COMPAT=y CONFIG_HIBERNATION=y CONFIG_PM_STD_PARTITION="/dev/sda7" CONFIG_PM_AUTOSLEEP=y CONFIG_PM_WAKELOCKS=y CONFIG_PM_WAKELOCKS_LIMIT=0 Loading drivers/iommu/arm-smmu.c +0 −13 Original line number Diff line number Diff line Loading @@ -524,11 +524,6 @@ static void arm_smmu_secure_domain_unlock(struct arm_smmu_domain *smmu_domain) mutex_unlock(&smmu_domain->assign_lock); } static bool arm_smmu_opt_hibernation(struct arm_smmu_device *smmu) { return IS_ENABLED(CONFIG_HIBERNATION); } #ifdef CONFIG_ARM_SMMU_SELFTEST static int selftest; Loading Loading @@ -1915,14 +1910,6 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, goto out_unlock; } if (arm_smmu_has_secure_vmid(smmu_domain) && arm_smmu_opt_hibernation(smmu)) { dev_err(smmu->dev, "Secure usecases not supported with hibernation\n"); ret = -EPERM; goto out_unlock; } /* * Mapping the requested stage onto what we support is surprisingly * complicated, mainly because the spec allows S1+S2 SMMUs without Loading Loading
arch/arm64/configs/vendor/sa8155_defconfig +2 −0 Original line number Diff line number Diff line Loading @@ -86,6 +86,8 @@ CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y CONFIG_BUILD_ARM64_UNCOMPRESSED_KERNEL=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_COMPAT=y CONFIG_HIBERNATION=y CONFIG_PM_STD_PARTITION="/dev/sda7" CONFIG_PM_AUTOSLEEP=y CONFIG_PM_WAKELOCKS=y CONFIG_PM_WAKELOCKS_LIMIT=0 Loading
drivers/iommu/arm-smmu.c +0 −13 Original line number Diff line number Diff line Loading @@ -524,11 +524,6 @@ static void arm_smmu_secure_domain_unlock(struct arm_smmu_domain *smmu_domain) mutex_unlock(&smmu_domain->assign_lock); } static bool arm_smmu_opt_hibernation(struct arm_smmu_device *smmu) { return IS_ENABLED(CONFIG_HIBERNATION); } #ifdef CONFIG_ARM_SMMU_SELFTEST static int selftest; Loading Loading @@ -1915,14 +1910,6 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, goto out_unlock; } if (arm_smmu_has_secure_vmid(smmu_domain) && arm_smmu_opt_hibernation(smmu)) { dev_err(smmu->dev, "Secure usecases not supported with hibernation\n"); ret = -EPERM; goto out_unlock; } /* * Mapping the requested stage onto what we support is surprisingly * complicated, mainly because the spec allows S1+S2 SMMUs without Loading