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Commit 0c1d40f5 authored by Jilai Wang's avatar Jilai Wang
Browse files

npu: Save and restore BWMON registers 



NPU driver needs to save/restore some BWMON registers when
suspend/resume bw monitor device.

Change-Id: Id7f54bdf1d8d4dfad54d421dad22123db8e610cb
Signed-off-by: default avatarJilai Wang <jilaiw@codeaurora.org>
parent 76f60b6d

drivers/media/platform/msm/npu/npu_common.h

+12 −0
Original line number Diff line number Diff line
@@ -136,6 +136,18 @@ struct npu_pwrlevel { 
	long clk_freq[NUM_TOTAL_CLKS];

};



/*

 * struct npu_reg - Struct holding npu register information

 * @ off - register offset

 * @ val - register value

 * @ valid - if register value is valid

 */

struct npu_reg {

	uint32_t off;

	uint32_t val;

	bool valid;

};



/**

 * struct npu_pwrctrl - Power control settings for a NPU device

 * @pwr_vote_num - voting information for power enable

drivers/media/platform/msm/npu/npu_dev.c

+35 −0
Original line number Diff line number Diff line
@@ -146,6 +146,15 @@ static const char * const npu_exclude_rate_clocks[] = { 
	"bto_core_clk"

};



static struct npu_reg npu_saved_bw_registers[] = {

	{ BWMON2_SAMPLING_WINDOW, 0, false },

	{ BWMON2_BYTE_COUNT_THRESHOLD_HIGH, 0, false },

	{ BWMON2_BYTE_COUNT_THRESHOLD_MEDIUM, 0, false },

	{ BWMON2_BYTE_COUNT_THRESHOLD_LOW, 0, false },

	{ BWMON2_ZONE_ACTIONS, 0, false },

	{ BWMON2_ZONE_COUNT_THRESHOLD, 0, false },

};



/* -------------------------------------------------------------------------

 * Entry Points for Probe

 * -------------------------------------------------------------------------
@@ -406,6 +415,30 @@ int npu_set_uc_power_level(struct npu_device *npu_dev, 
 * Bandwidth Related

 * -------------------------------------------------------------------------

 */

static void npu_save_bw_registers(struct npu_device *npu_dev)

{

	int i;



	for (i = 0; i < ARRAY_SIZE(npu_saved_bw_registers); i++) {

		npu_saved_bw_registers[i].val = REGR(npu_dev,

			npu_saved_bw_registers[i].off);

		npu_saved_bw_registers[i].valid = true;

	}

}



static void npu_restore_bw_registers(struct npu_device *npu_dev)

{

	int i;



	for (i = 0; i < ARRAY_SIZE(npu_saved_bw_registers); i++) {

		if (npu_saved_bw_registers[i].valid) {

			REGW(npu_dev, npu_saved_bw_registers[i].off,

				npu_saved_bw_registers[i].val);

			npu_saved_bw_registers[i].valid = false;

		}

	}

}



static void npu_suspend_devbw(struct npu_device *npu_dev)

{

	struct npu_pwrctrl *pwr = &npu_dev->pwrctrl;
@@ -417,6 +450,7 @@ static void npu_suspend_devbw(struct npu_device *npu_dev) 
		if (ret)

			pr_err("devfreq_suspend_devbw failed rc:%d\n",

				ret);

		npu_save_bw_registers(npu_dev);

	}

}
@@ -427,6 +461,7 @@ static void npu_resume_devbw(struct npu_device *npu_dev) 


	if (!pwr->bwmon_enabled) {

		pwr->bwmon_enabled = 1;

		npu_restore_bw_registers(npu_dev);

		ret = devfreq_resume_devbw(pwr->devbw);



		if (ret)

drivers/media/platform/msm/npu/npu_hw.h

+7 −0
Original line number Diff line number Diff line
@@ -31,6 +31,13 @@ 
#define NPU_GPR14 (0x00100138)

#define NPU_GPR15 (0x0010013C)



#define BWMON2_SAMPLING_WINDOW (0x001605A8)

#define BWMON2_BYTE_COUNT_THRESHOLD_HIGH (0x001605AC)

#define BWMON2_BYTE_COUNT_THRESHOLD_MEDIUM (0x001605B0)

#define BWMON2_BYTE_COUNT_THRESHOLD_LOW (0x001605B4)

#define BWMON2_ZONE_ACTIONS (0x001605B8)

#define BWMON2_ZONE_COUNT_THRESHOLD (0x001605BC)



#define CAL_DP_DMA_WR_RLD_CMD_0 (0x00580000)

#define CAL_DP_DMA_RD_RLD_CMD_0 (0x00580004)

#define CAL_DP_DMA_RD_RLD_CMD_1 (0x00580008)