Loading arch/arm64/boot/dts/qcom/sm6150-sde.dtsi +3 −3 Original line number Diff line number Diff line Loading @@ -474,17 +474,17 @@ <0x88e9000 0x17c>, <0x88e9400 0x10c>, <0x88e9800 0x10c>, <0xaf02000 0x1a0>, <0xaf02130 0x8>, <0x780000 0x621c>, <0x88e9c30 0x10>, <0xaee1000 0x34>, <0x1fcb200 0x50>, <0x1fcb24c 0x4>, <0xae91000 0x098>; /* dp_ctrl: dp_ahb, dp_aux, dp_link, dp_p0 */ reg-names = "dp_ahb", "dp_aux", "dp_link", "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", "dp_mmss_cc", "qfprom_physical", "dp_pll", "dp_pixel_mn", "qfprom_physical", "dp_pll", "hdcp_physical", "dp_tcsr","dp_p1"; interrupt-parent = <&mdss_mdp>; Loading drivers/gpu/drm/msm/dp/dp_catalog.c +3 −0 Original line number Diff line number Diff line Loading @@ -87,6 +87,7 @@ struct dp_catalog_io { struct dp_io_data *hdcp_physical; struct dp_io_data *dp_p1; struct dp_io_data *dp_tcsr; struct dp_io_data *dp_pixel_mn; }; /* audio related catalog functions */ Loading Loading @@ -2386,6 +2387,7 @@ static void dp_catalog_get_io_buf(struct dp_catalog_private *catalog) dp_catalog_fill_io_buf(hdcp_physical); dp_catalog_fill_io_buf(dp_p1); dp_catalog_fill_io_buf(dp_tcsr); dp_catalog_fill_io_buf(dp_pixel_mn); } static void dp_catalog_get_io(struct dp_catalog_private *catalog) Loading @@ -2405,6 +2407,7 @@ static void dp_catalog_get_io(struct dp_catalog_private *catalog) dp_catalog_fill_io(hdcp_physical); dp_catalog_fill_io(dp_p1); dp_catalog_fill_io(dp_tcsr); dp_catalog_fill_io(dp_pixel_mn); } static void dp_catalog_set_exe_mode(struct dp_catalog *dp_catalog, char *mode) Loading drivers/gpu/drm/msm/dp/dp_catalog_v200.c +7 −20 Original line number Diff line number Diff line Loading @@ -39,6 +39,7 @@ struct dp_catalog_io { struct dp_io_data *hdcp_physical; struct dp_io_data *dp_p1; struct dp_io_data *dp_tcsr; struct dp_io_data *dp_pixel_mn; }; struct dp_catalog_private_v200 { Loading Loading @@ -106,7 +107,7 @@ static void dp_catalog_aux_setup_v200(struct dp_catalog_aux *aux, wmb(); /* make sure programming happened */ io_data = catalog->io->dp_tcsr; dp_write(catalog->exe_mode, io_data, 0x4c, 0x1); /* bit 0 & 2 */ dp_write(catalog->exe_mode, io_data, 0x0, 0x1); wmb(); /* make sure programming happened */ io_data = catalog->io->dp_phy; Loading Loading @@ -136,8 +137,6 @@ static void dp_catalog_panel_config_msa_v200(struct dp_catalog_panel *panel, u32 const link_rate_hbr3 = 810000; struct dp_catalog_private_v200 *catalog; struct dp_io_data *io_data; u32 strm_reg_off = 0; u32 mvid_reg_off = 0, nvid_reg_off = 0; if (!panel) { pr_err("invalid input\n"); Loading @@ -150,16 +149,11 @@ static void dp_catalog_panel_config_msa_v200(struct dp_catalog_panel *panel, } catalog = dp_catalog_get_priv_v200(panel); io_data = catalog->io->dp_mmss_cc; if (panel->stream_id == DP_STREAM_1) strm_reg_off = MMSS_DP_PIXEL1_M_V200 - MMSS_DP_PIXEL_M_V200; io_data = catalog->io->dp_pixel_mn; pixel_m = dp_read(catalog->exe_mode, io_data, MMSS_DP_PIXEL_M_V200 + strm_reg_off); pixel_n = dp_read(catalog->exe_mode, io_data, MMSS_DP_PIXEL_N_V200 + strm_reg_off); pixel_m = dp_read(catalog->exe_mode, io_data, 0x0); pixel_n = dp_read(catalog->exe_mode, io_data, 0x4); pr_debug("pixel_m=0x%x, pixel_n=0x%x\n", pixel_m, pixel_n); mvid = (pixel_m & 0xFFFF) * 5; Loading @@ -186,16 +180,9 @@ static void dp_catalog_panel_config_msa_v200(struct dp_catalog_panel *panel, io_data = catalog->io->dp_link; if (panel->stream_id == DP_STREAM_1) { mvid_reg_off = DP1_SOFTWARE_MVID - DP_SOFTWARE_MVID; nvid_reg_off = DP1_SOFTWARE_NVID - DP_SOFTWARE_NVID; } pr_debug("mvid=0x%x, nvid=0x%x\n", mvid, nvid); dp_write(catalog->exe_mode, io_data, DP_SOFTWARE_MVID + mvid_reg_off, mvid); dp_write(catalog->exe_mode, io_data, DP_SOFTWARE_NVID + nvid_reg_off, nvid); dp_write(catalog->exe_mode, io_data, DP_SOFTWARE_MVID, mvid); dp_write(catalog->exe_mode, io_data, DP_SOFTWARE_NVID, nvid); } static void dp_catalog_ctrl_lane_mapping_v200(struct dp_catalog_ctrl *ctrl, Loading drivers/gpu/drm/msm/dp/dp_reg.h +0 −4 Original line number Diff line number Diff line Loading @@ -376,10 +376,6 @@ #define MMSS_DP_PIXEL_N (0x01B8) #define MMSS_DP_PIXEL1_M (0x01CC) #define MMSS_DP_PIXEL1_N (0x01D0) #define MMSS_DP_PIXEL_M_V200 (0x0130) #define MMSS_DP_PIXEL_N_V200 (0x0134) #define MMSS_DP_PIXEL1_M_V200 (0x0148) #define MMSS_DP_PIXEL1_N_V200 (0x014C) #define MMSS_DP_PIXEL_M_V420 (0x01B4) #define MMSS_DP_PIXEL_N_V420 (0x01B8) #define MMSS_DP_PIXEL1_M_V420 (0x01CC) Loading Loading
arch/arm64/boot/dts/qcom/sm6150-sde.dtsi +3 −3 Original line number Diff line number Diff line Loading @@ -474,17 +474,17 @@ <0x88e9000 0x17c>, <0x88e9400 0x10c>, <0x88e9800 0x10c>, <0xaf02000 0x1a0>, <0xaf02130 0x8>, <0x780000 0x621c>, <0x88e9c30 0x10>, <0xaee1000 0x34>, <0x1fcb200 0x50>, <0x1fcb24c 0x4>, <0xae91000 0x098>; /* dp_ctrl: dp_ahb, dp_aux, dp_link, dp_p0 */ reg-names = "dp_ahb", "dp_aux", "dp_link", "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", "dp_mmss_cc", "qfprom_physical", "dp_pll", "dp_pixel_mn", "qfprom_physical", "dp_pll", "hdcp_physical", "dp_tcsr","dp_p1"; interrupt-parent = <&mdss_mdp>; Loading
drivers/gpu/drm/msm/dp/dp_catalog.c +3 −0 Original line number Diff line number Diff line Loading @@ -87,6 +87,7 @@ struct dp_catalog_io { struct dp_io_data *hdcp_physical; struct dp_io_data *dp_p1; struct dp_io_data *dp_tcsr; struct dp_io_data *dp_pixel_mn; }; /* audio related catalog functions */ Loading Loading @@ -2386,6 +2387,7 @@ static void dp_catalog_get_io_buf(struct dp_catalog_private *catalog) dp_catalog_fill_io_buf(hdcp_physical); dp_catalog_fill_io_buf(dp_p1); dp_catalog_fill_io_buf(dp_tcsr); dp_catalog_fill_io_buf(dp_pixel_mn); } static void dp_catalog_get_io(struct dp_catalog_private *catalog) Loading @@ -2405,6 +2407,7 @@ static void dp_catalog_get_io(struct dp_catalog_private *catalog) dp_catalog_fill_io(hdcp_physical); dp_catalog_fill_io(dp_p1); dp_catalog_fill_io(dp_tcsr); dp_catalog_fill_io(dp_pixel_mn); } static void dp_catalog_set_exe_mode(struct dp_catalog *dp_catalog, char *mode) Loading
drivers/gpu/drm/msm/dp/dp_catalog_v200.c +7 −20 Original line number Diff line number Diff line Loading @@ -39,6 +39,7 @@ struct dp_catalog_io { struct dp_io_data *hdcp_physical; struct dp_io_data *dp_p1; struct dp_io_data *dp_tcsr; struct dp_io_data *dp_pixel_mn; }; struct dp_catalog_private_v200 { Loading Loading @@ -106,7 +107,7 @@ static void dp_catalog_aux_setup_v200(struct dp_catalog_aux *aux, wmb(); /* make sure programming happened */ io_data = catalog->io->dp_tcsr; dp_write(catalog->exe_mode, io_data, 0x4c, 0x1); /* bit 0 & 2 */ dp_write(catalog->exe_mode, io_data, 0x0, 0x1); wmb(); /* make sure programming happened */ io_data = catalog->io->dp_phy; Loading Loading @@ -136,8 +137,6 @@ static void dp_catalog_panel_config_msa_v200(struct dp_catalog_panel *panel, u32 const link_rate_hbr3 = 810000; struct dp_catalog_private_v200 *catalog; struct dp_io_data *io_data; u32 strm_reg_off = 0; u32 mvid_reg_off = 0, nvid_reg_off = 0; if (!panel) { pr_err("invalid input\n"); Loading @@ -150,16 +149,11 @@ static void dp_catalog_panel_config_msa_v200(struct dp_catalog_panel *panel, } catalog = dp_catalog_get_priv_v200(panel); io_data = catalog->io->dp_mmss_cc; if (panel->stream_id == DP_STREAM_1) strm_reg_off = MMSS_DP_PIXEL1_M_V200 - MMSS_DP_PIXEL_M_V200; io_data = catalog->io->dp_pixel_mn; pixel_m = dp_read(catalog->exe_mode, io_data, MMSS_DP_PIXEL_M_V200 + strm_reg_off); pixel_n = dp_read(catalog->exe_mode, io_data, MMSS_DP_PIXEL_N_V200 + strm_reg_off); pixel_m = dp_read(catalog->exe_mode, io_data, 0x0); pixel_n = dp_read(catalog->exe_mode, io_data, 0x4); pr_debug("pixel_m=0x%x, pixel_n=0x%x\n", pixel_m, pixel_n); mvid = (pixel_m & 0xFFFF) * 5; Loading @@ -186,16 +180,9 @@ static void dp_catalog_panel_config_msa_v200(struct dp_catalog_panel *panel, io_data = catalog->io->dp_link; if (panel->stream_id == DP_STREAM_1) { mvid_reg_off = DP1_SOFTWARE_MVID - DP_SOFTWARE_MVID; nvid_reg_off = DP1_SOFTWARE_NVID - DP_SOFTWARE_NVID; } pr_debug("mvid=0x%x, nvid=0x%x\n", mvid, nvid); dp_write(catalog->exe_mode, io_data, DP_SOFTWARE_MVID + mvid_reg_off, mvid); dp_write(catalog->exe_mode, io_data, DP_SOFTWARE_NVID + nvid_reg_off, nvid); dp_write(catalog->exe_mode, io_data, DP_SOFTWARE_MVID, mvid); dp_write(catalog->exe_mode, io_data, DP_SOFTWARE_NVID, nvid); } static void dp_catalog_ctrl_lane_mapping_v200(struct dp_catalog_ctrl *ctrl, Loading
drivers/gpu/drm/msm/dp/dp_reg.h +0 −4 Original line number Diff line number Diff line Loading @@ -376,10 +376,6 @@ #define MMSS_DP_PIXEL_N (0x01B8) #define MMSS_DP_PIXEL1_M (0x01CC) #define MMSS_DP_PIXEL1_N (0x01D0) #define MMSS_DP_PIXEL_M_V200 (0x0130) #define MMSS_DP_PIXEL_N_V200 (0x0134) #define MMSS_DP_PIXEL1_M_V200 (0x0148) #define MMSS_DP_PIXEL1_N_V200 (0x014C) #define MMSS_DP_PIXEL_M_V420 (0x01B4) #define MMSS_DP_PIXEL_N_V420 (0x01B8) #define MMSS_DP_PIXEL1_M_V420 (0x01CC) Loading