Commit 0bc2e2b5 authored Jul 20, 2018 by Srinivas Ramana Committed by Gerrit - the friendly Code Review server Jul 31, 2018

ARM: dts: msm: Add llcc cache dump support for sm6150



sm6150 supports a single instance Last level cache controller
with 256KB system cache. Add dump size to allocate buffers
for llcc cache dumps.

Change-Id: I86adc793df960667f623a5e8853e5b2b824b9ec3
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>

parent 0b3ec9bc

arch/arm64/boot/dts/qcom/sm6150.dtsi

+9 −0

Original line number	Diff line number	Diff line
		@@ -1105,6 +1105,11 @@
		qcom,dump-node = <&L2_TLB_700>;
		qcom,dump-id = <0x127>;
		};

		qcom,llcc1_d_cache {
		qcom,dump-node = <&LLCC_1>;
		qcom,dump-id = <0x140>;
		};
		};

		apps_rsc: mailbox@18220000 {
		@@ -1179,6 +1184,10 @@
		qcom,llcc-amon {
		compatible = "qcom,llcc-amon";
		};

		LLCC_1: llcc_1_dcache {
		qcom,dump-size = <0x6c000>;
		};
		};

		sdhc_1: sdhci@7c4000 {