Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0bba21ec authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: rename coresight DDR CTI name for sm8150"

parents f6ffc484 1eb2a19e

arch/arm64/boot/dts/qcom/sm8150-coresight.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -1890,7 +1890,7 @@ 
		reg = <0x6a02000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-ddr_dl_0_cti0";

		coresight-name = "coresight-cti-ddr_dl_0_cti_0";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1902,7 +1902,7 @@ 
		reg = <0x6a03000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-ddr_dl_0_cti1";

		coresight-name = "coresight-cti-ddr_dl_0_cti_1";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1914,7 +1914,7 @@ 
		reg = <0x6a10000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-ddr_dl_1_cti0";

		coresight-name = "coresight-cti-ddr_dl_1_cti_0";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1926,7 +1926,7 @@ 
		reg = <0x6a11000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-ddr_dl_1_cti1";

		coresight-name = "coresight-cti-ddr_dl_1_cti_1";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";